verilog inout problem

[fox34]

I try to convert vhdl code to verilog in vhdl I have :
sig0 <= sig_in; -- sig_in is inout

top : block
port map(
inout_sig => sig0
);
when inout_sig is inout type.

how to convert it to verilog?

 

[mk]

On 30 Apr 2006 08:29:05 -0700, "fox34" <zgluzer@nds.com> wrote:

I try to convert vhdl code to verilog in vhdl I have :
sig0 <= sig_in; -- sig_in is inout

top : block
port map(
inout_sig => sig0
);
when inout_sig is inout type.

how to convert it to verilog?

module top(rd_sig, wr_sig, inout_sig,...);
input rd_sig, wr_sig;
inout inout_sig;

wire sig_in = inout_sig;

wire oe_sig = rd_sig & !wr_sig;

reg sig_out;
wire inout_sig = oe_sig ? sig_out : 1'bZ;

oe_sig is high when data is to be output, it can be also a read signal
into top. you can simplify the oe_sig calculation and use only one of
the conditions or generate it internally.

 

[fox34]

mk כתב:

On 30 Apr 2006 08:29:05 -0700, "fox34" <zgluzer@nds.com> wrote:
module top(rd_sig, wr_sig, inout_sig,...);
input rd_sig, wr_sig;
inout inout_sig;

wire sig_in = inout_sig;

wire oe_sig = rd_sig & !wr_sig;

reg sig_out;
wire inout_sig = oe_sig ? sig_out : 1'bZ;

oe_sig is high when data is to be output, it can be also a read signal
into top. you can simplify the oe_sig calculation and use only one of
the conditions or generate it internally.

the problem is there are no rd or wr signals but only that logic , so I
can't use your solution.