Verilog (include) to VHDL (....) problem

[Luc]

Hi,

I have a reference design in Verilog, that I'm translating in VHDL.
The problem is that the Verilog design uses 'include files to load
some parameters.
If it were real numbers, I guess this won't be a big issue as one can
use CONSTANT .... in stead.
The problem is that the Verilog file uses a form like

parameter CLK_WAIT = (CLK_tPD <3) ? 0 : CLK_tPD - 3);

translating in something like :
if( CLK-tPD < 3) then 0 ELSE (CLK-tPD -3)

but as far as I know this can't be done in VHDL, simple
multiplications or divisions yes, but decisive ... I don't know

Any Ideas are much apreciated

Best regards,

Luc

 

[Allan Herriman]

On Mon, 26 Jul 2004 08:20:21 GMT, Luc <lb.edc@pandora.be> wrote:

Hi,

I have a reference design in Verilog, that I'm translating in VHDL.
The problem is that the Verilog design uses 'include files to load
some parameters.
If it were real numbers, I guess this won't be a big issue as one can
use CONSTANT .... in stead.
The problem is that the Verilog file uses a form like

parameter CLK_WAIT = (CLK_tPD <3) ? 0 : CLK_tPD - 3);

translating in something like :
if( CLK-tPD < 3) then 0 ELSE (CLK-tPD -3)

but as far as I know this can't be done in VHDL, simple
multiplications or divisions yes, but decisive ... I don't know

Any Ideas are much apreciated

This is a fault in VHDL that will (may?) be fixed in the next revision
(when you will be able to type:

constant CLK_WAIT = 0 when CLK_tPD < 3 else CLK_tPD - 3;

). In the meantime, you can create a function:

pure function make_CLK_WAIT returns integer is
begin
if( CLK-tPD < 3) then
return 0;
ELSE
return (CLK-tPD -3);
end if;
end make_CLK_WAIT;

constant CLK_WAIT = make_CLK_WAIT();

Regards,
Allan.

 

[Allan Herriman]

On Mon, 26 Jul 2004 18:41:20 +1000, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

On Mon, 26 Jul 2004 08:20:21 GMT, Luc <lb.edc@pandora.be> wrote:

Uuurgh. I've been using Verilog too much recently. That should have
been:

constant CLK_WAIT : integer := make_CLK_WAIT();

Regards,
Allan.

 

[Jonathan Bromley]

On Mon, 26 Jul 2004 18:46:29 +1000, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

Uuurgh. I've been using Verilog too much recently.

It's an occupational hazard

The OP's question set me thinking, though: lack of the
conditional ?: operator in VHDL-93 is a tad irritating.
So let's fix it...

function expr_if (
condition : boolean;
value_if_true : integer;
value_if_false : integer
) return integer is
begin
if condition then
return value_if_true;
else
return value_if_false;
end if;
end;

and then overload to your heart's content for all sorts
of other data types.

Then we can say

constant CLK_WAIT: integer :=
expr_if( CLK_tPD < 3, 0 , CLK_tPD - 3);

Sheesh, we're starting to make it look just like Excel :-(

Don't even think about type templates/generics.
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[Allan Herriman]

See also IEEE 200X Fast Track Change Proposal FT10B
http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/ft10B_sequential_assignment.pdf

I think they made a mistake: it only seems to apply to signal
assignment and won't work in a declarative region
I may be misinterpreting the document though.

Regards,
Allan.

 

[Jim Lewis]

Allan,
What you want is FT10A:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/ft10A_nnary.pdf

I split them out into separate items. FT10B is
good for lanugage consistency across concurrent
and sequential statements, however, in light of
FT10A, I am thinking that I will always use
the proposed n-nary expressions and never again use
the format of conditional signal assignment.
So that leads me to, should we do FT10B or not?
When we ask vendors for more features, we need to
make sure we can justify them by using them.

Note for FT10A, I orignally tried to make the syntax
work in a way that it would be identical to conditional
signal assignment. It is not possible to achieve the
consistency I wanted, so we came up with a different
syntax.

Cheers,
Jim

See also IEEE 200X Fast Track Change Proposal FT10B
http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/ft10B_sequential_assignment.pdf

I think they made a mistake: it only seems to apply to signal
assignment and won't work in a declarative region
I may be misinterpreting the document though.

Regards,
Allan.

--
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Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
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1-503-590-4787

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