Verilog in Signal Processing !!

[dash82]

Hi ,


I have been searching for "Root raised cosine filter" (http://
en.wikipedia.org/wiki/Raised-cosine_filter) implementation in Verilog.
I need to modulate my digital bits and hence need a raised cosine
filter.

I have been trying to implement it, but have been unsuccesful.

Could you provide any help on the same ?

Also, is there any good reference source for Verilog for Signal
Processing ?


Thanks.

-Shah..

 

[Mike Treseler]

dash82 wrote:

I have been searching for "Root raised cosine filter" (http://
en.wikipedia.org/wiki/Raised-cosine_filter) implementation in Verilog.
I need to modulate my digital bits and hence need a raised cosine
filter.

I would consider using myhdl to prototype the idea and
to generate the verilog code.
Here is a related example:
http://myhdl.jandecaluwe.com/doku.php/cookbook:sinecomp


-- Mike Treseler

 

[dash82]

On Nov 4, 8:40 am, Mike Treseler <mike_trese...@comcast.net> wrote:

dash82 wrote:
I have been searching for "Root raised cosine filter" (http://
en.wikipedia.org/wiki/Raised-cosine_filter) implementation in Verilog.
I need to modulate my digital bits and hence need a raised cosine
filter.

I would consider using myhdl to prototype the idea and
to generate the verilog code.
Here is a related example:http://myhdl.jandecaluwe.com/doku.php/cookbook:sinecomp

-- Mike Treseler

Thanks.