Verilog import in icfb

Hi all,

When I import RTL Verilog HDL in icfb to do an AMS simulation.

I have to declare this

`define IN_WIDTH 3
module test
#(parameter IN_WIDTH = 3)
(
input [`IN_WIDTH-1:0] data ....

If I do not put the define statement, icfb cannot inmport (unresolved
bus size), it seems to not take into account the by default value 3 of
the parameter IN_WIDTH...

Then when I import with the define statement, I have a correct
functional verilog model and symbol view in icfb BUT it removes in the
functional viwew (the verilog code view) the define statement and I
cannot simulate in AMS setup...

Do you have any idea how to facing this issue ?

THX.
Patrick

 

[Andrew Beckett]

fpgaasicdesigner@gmail.com wrote, on 04/10/09 18:09:

Hi all,

When I import RTL Verilog HDL in icfb to do an AMS simulation.

I have to declare this

`define IN_WIDTH 3
module test
#(parameter IN_WIDTH = 3)
(
input [`IN_WIDTH-1:0] data ....

If I do not put the define statement, icfb cannot inmport (unresolved
bus size), it seems to not take into account the by default value 3 of
the parameter IN_WIDTH...

Then when I import with the define statement, I have a correct
functional verilog model and symbol view in icfb BUT it removes in the
functional viwew (the verilog code view) the define statement and I
cannot simulate in AMS setup...

Do you have any idea how to facing this issue ?

THX.
Patrick

Hi Patrick,

Your code looks incorrect. You are mixing macros and parameters - the width of
the data bus is defined by the macro IN_WIDTH (because it is preceded by a
backtick), not by the parameter. From a bit of hunting around, I got this more
complete example:

module register2001 #(parameter SIZE=8)
(output reg [SIZE-1:0] q,
input [SIZE-1:0] d,
input clk, rst_n);
always @(posedge clk, negedge rst_n)
if (!rst_n) q <= 0;
else q <= d;
endmodule

And this imports fine in IC5141.

Otherwise, please give a more complete example, and the precise subversion
you're using - you certainly need to be using a version where ncvlog is used as
the analyzer rather than van because van did not support Verilog-2001. But
anything vaguely recent should be using ncvlog unless you've changed it locally
to use van instead.

Regards,

Andrew.