Verilog Implementation of FIR Filter

[gally]

On Feb 19, 5:34 pm, Rahul Iyer <rahul.hariha...@gmail.com> wrote:

HI,
I want the verilog implementation of N-Tap FIR filter.... I am bit in
a fix, to use a Distributed arithmetic or MAC unit... I suppose if I
am using Vertex 4 FPGA's that have inbuilt Multiplier, then I dont
need DA or MAC unit??
Kindly suggest...

Regards
Rahul

I think u can design by usin Matlab. There u can find a system
generate option in edatool design. You can design whichever filter u
want, and in which language u want, u can

 

[Rahul Iyer]

HI,
I want the verilog implementation of N-Tap FIR filter.... I am bit in
a fix, to use a Distributed arithmetic or MAC unit... I suppose if I
am using Vertex 4 FPGA's that have inbuilt Multiplier, then I dont
need DA or MAC unit??
Kindly suggest...

Regards
Rahul