Verilog if-else

[bir]

I have an issue regarding the if -else statement of verilog. I have my
next_st logic as below.

case (pres_st)

`IDLE : begin
if (tms==1'b0)
next_st = `IDLE;
else if (tms==1'b1)
next_st = `SEL_DR;
end
........
........

default : next_st = `IDLE

endcase

Everything worked fine here. But problem started when I slightly
modified my rtl. I replaced the "else if" statement to "else" impliying
that if its not "0" it should be "1".

case (pres_st)

`IDLE : begin
if (tms==1'b0)
next_st = `IDLE;
else
next_st = `SEL_DR;
end
........
........
default : next_st = `IDLE
endcase


Here I realized that during a particular instant in my test-bench, tms
was getting unassigned at IDLE st and my next state is getting assigned
with `SEL_DR.
Does that mean unassigned also falls into the else condition category?

Any suggestions?

Thanks

 

[Chris F Clark]

"bir" <ritwikbiswas@gmail.com> writes:

I have an issue regarding the if -else statement of verilog. I have my
next_st logic as below.

case (pres_st)

`IDLE : begin
if (tms==1'b0)
next_st = `IDLE;
else if (tms==1'b1)
next_st = `SEL_DR;
end
.......
.......

default : next_st = `IDLE

endcase

Everything worked fine here. But problem started when I slightly
modified my rtl. I replaced the "else if" statement to "else" impliying
that if its not "0" it should be "1".

case (pres_st)

`IDLE : begin
if (tms==1'b0)
next_st = `IDLE;
else
next_st = `SEL_DR;
end
.......
.......
default : next_st = `IDLE
endcase


Here I realized that during a particular instant in my test-bench, tms
was getting unassigned at IDLE st and my next state is getting assigned
with `SEL_DR.
Does that mean unassigned also falls into the else condition category?

Yes, both x and z values are not 0 (and they are also not 1).
Moreover, until you assign a value to a signal, its value is by
default x. In addition, certain other assignments can cause values to
become x. You don't generally want signals to be x once you've come
out of reset.

Any suggestions?

`IDLE : begin
if (tms==1'b0)
next_st = `IDLE;
else if (tms==1'b1)
next_st = `SEL_DR;
else

$display("ERROR: tms has the invalid value: ", tms );

end

Hope this helps,
-Chris

 

[Rajkumar Kadam]

Hi!
I would suggest you to look into why the tms signal went x, because
in real life it would go to any value, and lets say if it is not zero,
then
surely your state machine will trigger.
Normaly all the inputs should be driven with a valid value after reset.
Rajkumar...

Chris F Clark wrote:

"bir" <ritwikbiswas@gmail.com> writes:

I have an issue regarding the if -else statement of verilog. I have my
next_st logic as below.

case (pres_st)

`IDLE : begin
if (tms==1'b0)
next_st = `IDLE;
else if (tms==1'b1)
next_st = `SEL_DR;
end
.......
.......

default : next_st = `IDLE

endcase

Everything worked fine here. But problem started when I slightly
modified my rtl. I replaced the "else if" statement to "else" impliying
that if its not "0" it should be "1".

case (pres_st)

`IDLE : begin
if (tms==1'b0)
next_st = `IDLE;
else
next_st = `SEL_DR;
end
.......
.......
default : next_st = `IDLE
endcase


Here I realized that during a particular instant in my test-bench, tms
was getting unassigned at IDLE st and my next state is getting assigned
with `SEL_DR.
Does that mean unassigned also falls into the else condition category?

Yes, both x and z values are not 0 (and they are also not 1).
Moreover, until you assign a value to a signal, its value is by
default x. In addition, certain other assignments can cause values to
become x. You don't generally want signals to be x once you've come
out of reset.

Any suggestions?

`IDLE : begin
if (tms==1'b0)
next_st = `IDLE;
else if (tms==1'b1)
next_st = `SEL_DR;
else
$display("ERROR: tms has the invalid value: ", tms );
end

Hope this helps,
-Chris

 

[Ajeetha]

Normaly all the inputs should be driven with a valid value after reset.

To make sure that inputs are driven properly in simulation, one can use
a simple assertion check, for instance use:

assert_driven checker from SNPS SVA checker library, see:

http://www.synopsys.com/partners/tapin/forumpres/oct2004/svf/04_Synopsys_SystemVerilogForum.pdf

HTH
Ajeetha, CVC
www.noveldv.com