[Verilog] How to read data from a file?

[Davy]

I want to read one data per clock from a flie, and send them to a
pipelined circuit.
After that, save one data per clock to a file.

I am new to testbench. Now I decide to read a data (in) from file
@(negedge clk).
And pass this data to the module that I want to test @(posedge clk).
After that, save data (out) to a file. But my code seems to be wrong?

Is my test method right? Any suggestions will be appreciated!

//------code-----------
`define clk_cycle 10
module testbench_tb;

reg gclk;
integer os1,os2;
integer i,j;

wire [5:0] in;
reg [5:0] out;

initial begin
gclk = 0;
os1 = $fopen("tb_1.txt","r");
os2 = $fopen("tb_2.txt","w");
end

always # (`clk_cycle / 2) gclk = ~gclk;

always @ (negedge gclk)
begin
$fscanf(os1, "%d", in);
$fwrite(os2, "%d", out);
end

// pipelined circuit under test
always @ (posedge gclk)
begin
if(greset == 0)
begin
out <= 0;
end
else
begin
out <=in;
end
end
endmodule

Best regards,
Davy