Verilog HDL question (2)

Guest
How to show the gate-level circuit diagram after I write the following
statements?

"module test (A, B, C, D, Y);

input A, B, C, D;
output Y;

wire W1, W2, W3, W4;

nand #13 G1(W1, A, B);
not #10 G2(W2, C);
and #12 G3(W3, C, D);
nor #15 G4(W4, W1, W2);
or #12 G5(Y, W4, W3);

endmodule"



I don't know why it 's just show as belows:

nand #13 G1(W1, A, B);

Thanks a lot!
 
On Mar 22, 3:21 pm, bckcoo...@hotmail.com wrote:
How to show the gate-level circuit diagram after I write the following
statements?

"module test (A, B, C, D, Y);

input A, B, C, D;
output Y;

wire W1, W2, W3, W4;

nand #13 G1(W1, A, B);
not #10 G2(W2, C);
and #12 G3(W3, C, D);
nor #15 G4(W4, W1, W2);
or #12 G5(Y, W4, W3);

endmodule"

I don't know why it 's just show as belows:

nand #13 G1(W1, A, B);

Thanks a lot!
Click to expand...
use the syn tools
 
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