Verilog Generation

[Combinational Logic]

Rumor has it that Productivity Design Tools (www.productive-eda.com)
is soon to release a tool that is capable of producing RTL Verilog
given a higher-level specification. Any readers know anything about
PDT, the SPIRIT standard, or other related tools? What are your
thoughts on Electronics System Level (ESL) tools in general?

 

[Sandy]

Combinational Logic wrote:

Rumor has it that Productivity Design Tools (www.productive-eda.com)
is soon to release a tool that is capable of producing RTL Verilog
given a higher-level specification. Any readers know anything about
PDT, the SPIRIT standard, or other related tools? What are your
thoughts on Electronics System Level (ESL) tools in general?

I seriously think that ESL level design is the future of ASIC.
Like how people have migrated from gate-level to RTL level in a decade,
i would say in another few years everybody would have migrated to ESL.

 

[Vinilkant Tejaswi]

Dr. Arvind is a principal investigator from MIT with a start up company
called

www.bluespec.com

He has over 25-30 years of research in computer architecture and
developed data driven architectures called Monsoon architecture [just
some info]. The other company that might be of interest



http://www.beachsolutions.com/synthesis/esl_synthesis.htm