[Verilog] function problem?

[Davy]

Hi all,

I want to use function to write small combinational logic.
But I found it seems I cannot declear wire in function,why?
Any suggestions will be appreciated!

The func_test have some compile error, why?
//--------func_test---------------
module func_test(
in_1,
in_2,
in_3,
out,
);

input [5:0] in_1;
input [5:0] in_2;
input [5:0] in_3;

output [5:0] out;

assign out = plus(in_1,in_2,in_3);

function [5:0] plus;
input [5:0]in_1;
input [5:0]in_2;
input [5:0]in_3;
wire [5:0] plus;
begin
assign plus = in_1+in_2;
assign out = plus + in_3;
end
endfunction

endmodule

Best regards,
Davy