Verilog Function Declaration

[rookie]

Hi,

I'm wondering if following verilog function declaration is valid or
not, since it can be compiled succesfully in Modelsim & Synplify, but
failed in NC-verilog and VCS .

function reg [1:0] myfunc(input wire [1:0] data);
begin
if(data==2'b00)
myfunc = 2'b00;
else if(data==2'b01)
myfunc = 2'b01;
else if(data==2'b10)
myfunc = 2'b11;
else
myfunc = 2'b10;
end
endfunction

Thanks

 

On Oct 25, 2:12 am, rookie <baekhaery...@gmail.com> wrote:

Hi,

I'm wondering if following verilog function declaration is valid or
not, since it can be compiled succesfully in Modelsim & Synplify, but
failed in NC-verilog and VCS .

function reg [1:0] myfunc(input wire [1:0] data);

It is illegal. A function or task formal argument cannot be declared
to be a wire. The language grammar doesn't allow it, nor would it
make any sense. Passing a formal argument is equivalent to a
procedural assignment, which can only be done for variables, not
wires.