Verilog for VHDL (others => '0')?

[Pasacco]

Hi

In VHDL, when we assign value to signal a, we can use following:

// VHDL : assign all bits to zero
a <= (others => '0');

What is verilog syntax to do same?
Thank you in advance

 

[Mark McDougall]

Pasacco wrote:

In VHDL, when we assign value to signal a, we can use following:

// VHDL : assign all bits to zero
a <= (others => '0');

What is verilog syntax to do same?

Ummm, a = 0; should work for vectors up to 32 bits, no?

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[glen herrmannsfeldt]

Pasacco <pasacco@gmail.com> wrote:

In VHDL, when we assign value to signal a, we can use following:

// VHDL : assign all bits to zero
a <= (others => '0');

What is verilog syntax to do same?

I usually use continuous assignment in verilog, and use
concatenation to concatenate the appropriate number of zeros.

For behavioral assignment, can't you just assign zeros to
all bits first, and then write over them?

-- glen

 

[Muzaffer Kal]

On Thu, 22 Jan 2009 10:48:13 +1100, Mark McDougall <markm@vl.com.au>
wrote:

Pasacco wrote:

In VHDL, when we assign value to signal a, we can use following:

// VHDL : assign all bits to zero
a <= (others => '0');

What is verilog syntax to do same?

Ummm, a = 0; should work for vectors up to 32 bits, no?

Actually it's better than that. The bits of 'a' which are not
assigned by '0' are filled with zeros so 'a=0' is guaranteed to
initialize all bits of a to zero.

 

[Jason Zheng]

On Thu, 22 Jan 2009 10:48:13 +1100
Mark McDougall <markm@vl.com.au> wrote:

Pasacco wrote:

In VHDL, when we assign value to signal a, we can use following:

// VHDL : assign all bits to zero
a <= (others => '0');

What is verilog syntax to do same?

Ummm, a = 0; should work for vectors up to 32 bits, no?

Or a = { n {1'b0} } , where n is the width of a. This works for all

vector sizes.

--
"Here's something to think about: How come you never see a headline
like `Psychic Wins Lottery'?"
-- Jay Leno

 

[gabor]

On Jan 21, 7:24 pm, Jason Zheng <Xin.Zh...@jpl.nasa.gov> wrote:

On Thu, 22 Jan 2009 10:48:13 +1100

Mark McDougall <ma...@vl.com.au> wrote:
Pasacco wrote:

In VHDL, when we assign value to signal a, we can use following:

// VHDL : assign all bits to zero
a <= (others => '0');

What is verilog syntax to do same?

Ummm, a = 0; should work for vectors up to 32 bits, no?

Or a = { n {1'b0} } , where n is the width of a. This works for all
vector sizes.

The repeated vector notation also works where you
have:

a <= (others => '1');

i.e.

a = { n {1'b1} };

which is not as easily represented as zero.

--
"Here's something to think about:  How come you never see a headline
like `Psychic Wins Lottery'?"
                -- Jay Leno

I assume you would first need to declare:

`define Psychic actual_lottery_winner

then it follows:

`Psychic Wins Lottery

 

[Jonathan Bromley]

SystemVerilog offers the shorthand notations

'x
'z
'0
'1

to mean that the target word is filled with the
specified bit value. For example:

logic [127:0] wide_vec;
initial wide_vec = '1; // same as {128{1'b1}}
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
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