Verilog file inclusion

[gh]

I'm run into an interesting behavior of the ModelSim simulator, for
which I hope someone can identify the cause.

I have several source files which compile and simulate when I do the
following:

// some verilog code...
include "../foo.v";
// more verilog code


However, when I use the "correct" verilog directive:

`include "../foo.v"

I get Undefined variable errors for wires, registers, parameters, etc.
defined/declared in the included file. This is puzzling since the
contents of the included file are supposed to stricly replace the
`include declaration in the original source file.

Anyone experience a similar problem, or know what's wrong?

Thanks.

-gh

 

[snehashis]

hi friends,
i am facing a problem on readmemb.I dont know how to use the testbench
in xilinx environment.I am using xilinx ise 5.2 i and modelsim 5.7i.can
anybody please tell me how to compile my testbench in modelsim?so far i am
using only the gui.
the problem is in my testbench,i use readmemb to read from a file
which contains serial byte organised data as input.what extension should
the input file have?and where is it to be placed so that compiler
recognises it?i mean is it necessary to give full path or is it to be
placed in same directory of the project?
also i need to write the outputs in another file which is byte
organised.it will be very helpful if the exact syntax with arguments are
given,so that i write the serial outputs in another file..
thanking you,
snehashis

 

[Berty]

Can't help you with ModelSim as I don't use Modelsim however as for
the file to be read by the readmem the name is not important however if
the file is not place in local directory where you compile it you
should give the full path.

Since you use readmemb the value should be in binary and the width and
length should (though depend on the compiler it might forgive if you
don't obey this) the same as the size of the array to where you read
this file.

As for writing the result you can either open a file and write to it or
just send the value using regular display command where you also added
let say the word RESULT and than you simple grep the line with RESULT
from the verilog.log.

Have Fun.