Verilog exponential operator issues in simulation (ISE 7.1 S

[Nju Njoroge]

Hi,

I'm using the Verilog-2001 exponential operator to do the following:

`define NUM_COUNTER_BITS 8;
parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);

When I simulate this in ModelSim 6.0a, launched from Project Nav. (ISE
7.1 SP3), NUM_COUNTER_CYCLLES = 5. However, if I use a parameter for
NUM_COUNTER_BITS instead of `define, as shown below, NUM_COUNTER_CYCLES
= 256, which is the desired result.

parameter NUM_COUNTER_BITS = 8;
parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);

What are the inherent differences between a parameter and `define
directive that could this problem to occur.

Thanks,

NN

 

[Nju Njoroge]

Jason Zheng wrote:

Nju Njoroge wrote:
Hi,

I'm using the Verilog-2001 exponential operator to do the following:

`define NUM_COUNTER_BITS 8;
parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);

When I simulate this in ModelSim 6.0a, launched from Project Nav. (ISE
7.1 SP3), NUM_COUNTER_CYCLLES = 5. However, if I use a parameter for
NUM_COUNTER_BITS instead of `define, as shown below, NUM_COUNTER_CYCLES
= 256, which is the desired result.

parameter NUM_COUNTER_BITS = 8;
parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);

What are the inherent differences between a parameter and `define
directive that could this problem to occur.

I tried it with ncverilog, and didn't get the bad answer. Is it
posssible that the ; at the end of `define is causing the problem?

Try this in your module:

initial
$display ("NUM_COUNTER_BITS = %d", `NUM_COUNTER_BITS);
Thanks for the suggestion. I tried this below:

$display("NUM_COUNTER_CYCLES=%d", 2 ** `NUM_COUNTER_BITS);

and it does print out "NUM_COUNTER_CYCLES=256" in ModelSim. However, in
the actual waveform, the value is still 5 and the logic uses that
incorrect value.

The main reason I want to use `define directive is because I'm using a
`include file since this constant is used in many other modules.

NN

 

[Nju]

Nju Njoroge wrote:

Jason Zheng wrote:
Nju Njoroge wrote:
Hi,

I'm using the Verilog-2001 exponential operator to do the following:

`define NUM_COUNTER_BITS 8;
parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);

When I simulate this in ModelSim 6.0a, launched from Project Nav. (ISE
7.1 SP3), NUM_COUNTER_CYCLLES = 5. However, if I use a parameter for
NUM_COUNTER_BITS instead of `define, as shown below, NUM_COUNTER_CYCLES
= 256, which is the desired result.

parameter NUM_COUNTER_BITS = 8;
parameter NUM_COUNTER_CYCLES = 2 ** (`NUM_COUNTER_BITS);

What are the inherent differences between a parameter and `define
directive that could this problem to occur.

I tried it with ncverilog, and didn't get the bad answer. Is it
posssible that the ; at the end of `define is causing the problem?

Try this in your module:

initial
$display ("NUM_COUNTER_BITS = %d", `NUM_COUNTER_BITS);
Thanks for the suggestion. I tried this below:
$display("NUM_COUNTER_CYCLES=%d", 2 ** `NUM_COUNTER_BITS);

and it does print out "NUM_COUNTER_CYCLES=256" in ModelSim. However, in
the actual waveform, the value is still 5 and the logic uses that
incorrect value.

The main reason I want to use `define directive is because I'm using a
`include file since this constant is used in many other modules.

NN

By the way, the ";" at the end of the `define directive was a typo in
my original posting. I don't have it in the real code.

NN

 

[Andy Peters]

Nju Njoroge wrote:

Thanks for the suggestion. I tried this below:
$display("NUM_COUNTER_CYCLES=%d", 2 ** `NUM_COUNTER_BITS);

and it does print out "NUM_COUNTER_CYCLES=256" in ModelSim. However, in
the actual waveform, the value is still 5 and the logic uses that
incorrect value.

$display("NUM_COUNTER_CYCLES=%d", 2 ** `NUM_COUNTER_BITS);

isn't the same as:

$display("NUM_COUNTER_CYCLES=%d", NUM_COUNTER_CYCLES);

so maybe there's something else going on in your code?

The main reason I want to use `define directive is because I'm using a
`include file since this constant is used in many other modules.

Yeah, I've fought (and lost) that battle.

Another thing you could do is simply put the parameters on your tool's
command line. The two arguments against this are:

a) Some tools (like Xilinx XST) don't support setting parameters on the
command line, and
b) It's convenient to have the definitions for the particular build
available as a source file, rather than buried in a script somewhere.

The ideal is to be able to build different versions of your chip from
source without modifying the source. Sometimes practical issues get in
the way.

-a

 

[Andy Peters]

Marko wrote:

One difference is that parameters can be over-ridden by the calling
module via the defparam command. Not true with `define.

Some tools let you override `defines from the command line.

-a