Verilog Equivalent for VHDL Generic that is not set.

[Seanie]

Hi all,
I am new to verilog - i am having trouble using generics in Verilog. I
have a vhdl file which contains the following generic:

GENERIC(
abs_addr_width : Integer :=4;
abs_mpu_start : Integer
);

Can anyone tell me what the verilog equivalent is? I have tried the
verilog lines below but it will not compile.


parameter cwt_addr_width = 4;
parameter cwt_mpu_start ;

I do not want to set it to 0 as it then has a value.

Would appreciate any help
Thanks

 

[Chris F Clark]

Seanie wants to do something like:

parameter cwt_mpu_start ;

I do not want to set it to 0 as it then has a value.

You must give it some value in Verilog. there are no parameters that
are valueless. However, you might be able to give it an "invalid"
value, so that if the value was used without being overriden it would
stick out as "wrong".

parameter cwt_mpu_start = 1'bx; // x is traditionally used to denote undefined

Now, whether this will work or not depends on how cwt_mpu_start is
used. From it's name, it looks like it is used to initialize some
register, and in that case x is a good choice. If it is used instead
to size something, x may not be a good choice. Worse, if it is used
as a selection in a casex statement, x is a bad choice--although in
casez statements that problem is avoided.

casex(cwt_mpu)
cwt_mpu_start: // some action
//using cwt_mpu_start as 1'bx is bad here because it will match too much
endcase

Hope this helps,
-Chris

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