Verilog: "don't care" in

[mnentwig]

Hi,

is there any simple way to point out impossible cases in compariso
operators?
For example, I have the expression

result <= (value <= 17? ) ... : ...
I know that "value" is modulo-four, and 18, 19 are the only possible value
that give a true result.
In a "case" statement, "//synthesis full_case" does what I want, but i
seems rather clumsy.

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[Mark Curry]

In article <BMKdnRsPXp67W3fMnZ2dnUVZ_radnZ2d@giganews.com>,
mnentwig <24789@embeddedrelated> wrote:

is there any simple way to point out impossible cases in comparison
operators?
For example, I have the expression

result <= (value <= 17? ) ... : ...
I know that "value" is modulo-four, and 18, 19 are the only possible values
that give a true result.
In a "case" statement, "//synthesis full_case" does what I want, but it
seems rather clumsy.

I'd just code the easy things. Since you know it's modulo-4 then just mask
(or ignore) the lower two-bits. If you mean that inputs > 19 never occur, then
mask (or ignore) bits over bit 4.

Anything else usually isn't worth the effort. If there's any way the synthesis
tool can figure out this extra information, it'll do very good job at
optimizing it on it's own.

My 2 cents...

--Mark

 

[mnentwig]

Hi,

thanks for the reply.
Agree, I don't want to get stuck in micro-optimization. I was just hopin
for a simple solution like

// synthesis assume(value < 20)

(this is FAKE. I've made it up. Don't use it)

Theoretically, the synthesis tool could figure it out, but I doubt it'
that smart.

BTW, a mistake in my post: I meant modulo-20 (not 4). The _increment_ in m
example is 4, and the only cases that trigger the condition are

16+4
17+4
18+4
19+4


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On Tuesday, July 23, 2013 6:27:31 AM UTC-5, mnentwig wrote:

Theoretically, the synthesis tool could figure it out,
but I doubt it's that smart.

Synplify performs reachability analysis on counters and state machines. With that information, it will optimize comparisons to the count or state. Whether it can determine that some values are not reachable, I cannot tell from the information given.

Andy