Verilog delays in FPGAs

[Kieren Johnstone]

Hello there,

I am currently learning Verilog for use in experimenting with FPGAs -
namely the Pluto boards from www.fpga4fun.com. However after much
investigation I have been unable to find an explanation for statements
such as:

if (~aclr) wp <= #1 0;

I am referrering here to the "#1". I am to understand this means the
assignment / transfer should be delayed.. but I have only read that
this is a delay by one "simulation cycle". Does this mean that these
"#1"s are ignored when implemented on an FPGA?

If not, what do they do?

I would assume that somehow (magically?) all the 'regular' transfers
would occur first, then all the statements with a '#1', and so on (a
more asynchronous approach?).

I have tried my best to research this, but my lack of a good index of
appropriate sites and the fact my Verilog / FPGA books will take a few
more weeks to arrive has limited my progress.

Thanks for the help,
Kieren Johnstone

 

[Pablo Bleyer Kocik]

You can find a good discussion about using #1 delays with current
synthesis/simulation tools at
http://www.deepchip.com/items/0410-11.html.

Regards.

 

[John Providenza]

Kieren -
One of the things you need to know about Verilog is that some
of the language is not synthesizable and is only (currently?)
useful for simulation. The #delay constuct is one of the
'simulation' only aspects of the language. Some people
like to use
always @(posedge clk)
foo <= #1 bar;
so that when they look at waveforms in their simulator they can
see 'cause and effect', ie, clock happens, then flop outputs change.
If you leave the #1 out, it looks like both happen at the same time.

Personally, I don't use this 'feature'.

Delays are very useful when writing simulation models to achieve
setup or hold times as you generate stimulus to your actual design.

In general, as you code something in Verilog, you need to try to
imagine what it woud look like in H/W. If you can't imagine a
reasonable structure, the Verilog constructs you're using may not
be synthesizable.

The Xilinx documentation has info on what their XST synthesizer likes.

Good Luck!

John P.



kierenj@handtheband.com (Kieren Johnstone) wrote in message news:<cc50c20.0408221456.778befbf@posting.google.com>...

Hello there,

I am currently learning Verilog for use in experimenting with FPGAs -
namely the Pluto boards from www.fpga4fun.com. However after much
investigation I have been unable to find an explanation for statements
such as:

if (~aclr) wp <= #1 0;

I am referrering here to the "#1". I am to understand this means the
assignment / transfer should be delayed.. but I have only read that
this is a delay by one "simulation cycle". Does this mean that these
"#1"s are ignored when implemented on an FPGA?

If not, what do they do?

I would assume that somehow (magically?) all the 'regular' transfers
would occur first, then all the statements with a '#1', and so on (a
more asynchronous approach?).

I have tried my best to research this, but my lack of a good index of
appropriate sites and the fact my Verilog / FPGA books will take a few
more weeks to arrive has limited my progress.

Thanks for the help,
Kieren Johnstone