Verilog Custom Core To Read and Write From RAM

[aibk01]

I want to add a custom verilog core to an already established pipeline o
microblaze. The core should be able to read data from memory location
from DDR RAM (external) which is already present on PLB, process it i.e ad
to value of data and replace the data it has read with the new processe
data. In short i want to add certain constant number to data on RAM in
parallel fashion,(video frame) and write back to those very locations.

Please guide me how should i go about. Should i create a custo
peripheral?

Should i use FSL?

As i am new in this field kindly guide me!

Thank You


I am using Xilinx Spartan3E 1600.

With ISE and XPS 10.1 sp1



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[maxascent]

You can just do this with the Microblaze processor. Just read the valu
from memory, do what you want with it and then write it back. If you nee
to do it faster than this then you would need to write a custom IP block t
interface with the PLB bus that could read and write from memory.

Jon

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[maxascent]

Well i am trying to do the very same thing but i am having problems i
writing the user_logic file as i am accustomed only to verilog. Even i

verilog the custom_core.vhd file is in VHDL. I am having problems if an
one can guide me on that.

How should i manage, i have already put two registers in the core, one fo
reading data and other for writing.

Now can u guide me in configuring it so that it can read and writ
data.(verilog part)

When you generate a custom core in EDK, set the check box to create
Verilog template for the user logic. You can then write your logic i
Verilog.

Jon

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[Ali Iqbal]

Well i am trying to do the very same thing but i am having problems in writing the user_logic file as i am accustomed only to verilog. Even in verilog the custom_core.vhd file is in VHDL. I am having problems if any one can guide me on that.

How should i manage, i have already put two registers in the core, one for reading data and other for writing.

Now can u guide me in configuring it so that it can read and write data.(verilog part)

 

[aibk01]

Well i selected the Verilog thing and it generated user_logic in Verilog.


But now what i want to write to one register and read after adding
constant value to it. (I have used to registers).
What do i do with the sample code. Should i delete or modify it. But Ho
kindly guide.


i can post the code if it helps:


//----------------------------------------------------------------------------
// user_logic.v - module
//----------------------------------------------------------------------------
//
/
***************************************************************************
// ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
**
// **
**
// ** Xilinx, Inc.
**
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
**
// ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
**
// ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
**
// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
**
// ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
**
// ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
**
// ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
**
// ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
**
// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
**
// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
**
// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
**
// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
**
// ** FOR A PARTICULAR PURPOSE.
**
// **
**
/
***************************************************************************
//
//----------------------------------------------------------------------------
// Filename: user_logic.v
// Version: 1.00.a
// Description: User logic module.
// Date: Wed Jul 06 11:20:21 2011 (by Create and Impor
Peripheral Wizard)
// Verilog Standard: Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port: "*_i"
// device pins: "*_pin"
// ports: "- Names begin with Uppercase"
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------

module user_logic
(
// -- ADD USER PORTS BELOW THIS LINE ---------------
// --USER ports added here
// -- ADD USER PORTS ABOVE THIS LINE ---------------

// -- DO NOT EDIT BELOW THIS LINE ------------------
// -- Bus protocol ports, do not add to or delete
Bus2IP_Clk, // Bus to IP clock
Bus2IP_Reset, // Bus to IP reset
Bus2IP_Data, // Bus to IP data bus
Bus2IP_BE, // Bus to IP byte enables
Bus2IP_RdCE, // Bus to IP read chip enable
Bus2IP_WrCE, // Bus to IP write chip enable
IP2Bus_Data, // IP to Bus data bus
IP2Bus_RdAck, // IP to Bus read transfer
acknowledgement
IP2Bus_WrAck, // IP to Bus write transfer
acknowledgement
IP2Bus_Error // IP to Bus error response
// -- DO NOT EDIT ABOVE THIS LINE ------------------
); // user_logic

// -- ADD USER PARAMETERS BELOW THIS LINE ------------
// --USER parameters added here
// -- ADD USER PARAMETERS ABOVE THIS LINE ------------

// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol parameters, do not add to or delete
parameter C_SLV_DWIDTH = 32;
parameter C_NUM_REG = 2;
// -- DO NOT EDIT ABOVE THIS LINE --------------------

// -- ADD USER PORTS BELOW THIS LINE -----------------
// --USER ports added here
// -- ADD USER PORTS ABOVE THIS LINE -----------------

// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol ports, do not add to or delete
input Bus2IP_Clk;
input Bus2IP_Reset;
input [0 : C_SLV_DWIDTH-1] Bus2IP_Data;
input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE;
input [0 : C_NUM_REG-1] Bus2IP_RdCE;
input [0 : C_NUM_REG-1] Bus2IP_WrCE;
output [0 : C_SLV_DWIDTH-1] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
// -- DO NOT EDIT ABOVE THIS LINE --------------------

//----------------------------------------------------------------------------
// Implementation
//----------------------------------------------------------------------------

// --USER nets declarations added here, as needed for user logic

// Nets for user logic slave model s/w accessible register example
reg [0 : C_SLV_DWIDTH-1] slv_reg0;
reg [0 : C_SLV_DWIDTH-1] slv_reg1;
wire [0 : 1] slv_reg_write_sel;
wire [0 : 1] slv_reg_read_sel;
reg [0 : C_SLV_DWIDTH-1] slv_ip2bus_data;
wire slv_read_ack;
wire slv_write_ack;
integer byte_index, bit_index;

// --USER logic implementation added here

// ------------------------------------------------------
// Example code to read/write user logic slave model s/w accessible
registers
//
// Note:
// The example code presented here is to show you one way of
reading/writing
// software accessible registers implemented in the user logic slave
model.
// Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to
correspond
// to one software accessible register by the top level template. For
example,
// if you have four 32 bit software accessible registers in the user
logic,
// you are basically operating on the following memory mapped registers:
//
// Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
// "1000" C_BASEADDR + 0x0
// "0100" C_BASEADDR + 0x4
// "0010" C_BASEADDR + 0x8
// "0001" C_BASEADDR + 0xC
//
// ------------------------------------------------------

assign
slv_reg_write_sel = Bus2IP_WrCE[0:1],
slv_reg_read_sel = Bus2IP_RdCE[0:1],
slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1],
slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1];

// implement slave model register(s)
always @( posedge Bus2IP_Clk )
begin: SLAVE_REG_WRITE_PROC

if ( Bus2IP_Reset == 1 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
end
else
case ( slv_reg_write_sel )
2'b10 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1;
byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <=
byte_index*8+7; bit_index = bit_index+1 )
slv_reg0[bit_index] <= Bus2IP_Data[bit_index];
2'b01 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1;
byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <=
byte_index*8+7; bit_index = bit_index+1 )
slv_reg1[bit_index] <= Bus2IP_Data[bit_index];
default : ;
endcase

end // SLAVE_REG_WRITE_PROC

// implement slave model register read mux
always @( slv_reg_read_sel or slv_reg0 or slv_reg1 )
begin: SLAVE_REG_READ_PROC

case ( slv_reg_read_sel )
2'b10 : slv_ip2bus_data <= slv_reg0;
2'b01 : slv_ip2bus_data <= slv_reg1;
default : slv_ip2bus_data <= 0;
endcase

end // SLAVE_REG_READ_PROC

// ------------------------------------------------------------
// Example code to drive IP to Bus signals
// ------------------------------------------------------------

assign IP2Bus_Data = slv_ip2bus_data;
assign IP2Bus_WrAck = slv_write_ack;
assign IP2Bus_RdAck = slv_read_ack;
assign IP2Bus_Error = 0;

endmodule


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[RCIngham]

To help us keep accurate statistics, are you a lazy student or a clueles
would-be hobbyist?


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[maxascent]

You need to first understand how the IPIF works. You can't just expec
someone to learn it for you. Once you have the knowledge then it is simpl
to write your code in Verilog or VHDL.

Jon

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[aibk01]

To help us keep accurate statistics, are you a lazy student or a clueless
would-be hobbyist?


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Neither a lazy student nor a hobbyist



I am a student. It is easier to critique than to help some one. It was
easy question. I have not asked you to write down a code for me just aske
"Will I be requiring the sample code or can i replace it with my own lik
in Usual verilog codes".


I want really appreciate some help here.

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[aibk01]

Thank you Jon i will read about the IPIF for both PLB/OPB which ever i ca
use.If i face any problem i will ask.
Thanks again

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