Verilog concurrency code.. help out!

[spartan3wiz]

All verilog-experts can you help me with the following example? I'm a
happy hobbyist trying to grasp the most elemental part of verilog.
help me out! Has the code below a clear sense of flow, thus, is it
possible to say exactly what is going to happen in simulation? Is it
safe for Synthesizing into any technology? Is it safe for FPGAs? What
is the value after the first clock cycle,second clock cycle? Please
help me out..

-snip-
reg a = 1'b0;
reg b;
reg c;
always@(posedge clk)
begin
a <= 1'b01;
end
always@(posedge clk)
begin
b = a;
end
always@(posedge clk)
begin
c <= a;
end
-snip-

 

[Dwayne Dilbeck]

Not every synthesis tool will synthesize a default value for "reg a =
1'b0;".

As a result the synthesis is not garanteed to execute the same way that
simulation would. In simulation:

time #clk_cycle A B C
0 0 0 X X
X 1 1 0 0
X 2 1 1 1

I know of atleast one synthesis tool that would ignore the initial value, it
would then decide that the CLK is not needed, the final synthesized result
would not have any FF's just assign statements.

ie: assign A =1'b1;
assign B = A;
assign C = A;

That same synthesis tool can be told to keep all flip flops. In that case
the result would be

time #clk_cycle A B C
0 0 X X X
X 1 1 X X
X 2 1 1 1


"spartan3wiz" <magnus.wedmark@gmail.com> wrote in message
news:8de874fc-382b-4792-8b4b-7a587df13ecc@d4g2000prg.googlegroups.com...

All verilog-experts can you help me with the following example? I'm a
happy hobbyist trying to grasp the most elemental part of verilog.
help me out! Has the code below a clear sense of flow, thus, is it
possible to say exactly what is going to happen in simulation? Is it
safe for Synthesizing into any technology? Is it safe for FPGAs? What
is the value after the first clock cycle,second clock cycle? Please
help me out..

-snip-
reg a = 1'b0;
reg b;
reg c;
always@(posedge clk)
begin
a <= 1'b01;
end
always@(posedge clk)
begin
b = a;
end
always@(posedge clk)
begin
c <= a;
end
-snip-

 

[spartan3wiz]

On 14 Jan, 20:20, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote:

Not every synthesis tool will synthesize a default value for "reg a =
1'b0;".

As a result the synthesis is not garanteed to execute the same way that
simulation would. In simulation:

time #clk_cycle A B C
0 0 0 X X
X 1 1 0 0
X 2 1 1 1

I know of atleast one synthesis tool that would ignore the initial value, it
would then decide that the CLK is not needed, the final synthesized result
would not have any FF's just assign statements.

ie: assign A =1'b1;
assign B = A;
assign C = A;

That same synthesis tool can be told to keep all flip flops. In that case
the result would be

time #clk_cycle A B C
0 0 X X X
X 1 1 X X
X 2 1 1 1

"spartan3wiz" <magnus.wedm...@gmail.com> wrote in message

news:8de874fc-382b-4792-8b4b-7a587df13ecc@d4g2000prg.googlegroups.com...

All verilog-experts can you help me with the following example? I'm a
happy hobbyist trying to grasp the most elemental part of verilog.
help me out! Has the code below a clear sense of flow, thus, is it
possible to say exactly what is going to happen in simulation? Is it
safe for Synthesizing into any technology? Is it safe for FPGAs? What
is the value after the first clock cycle,second clock cycle? Please
help me out..

-snip-
reg a = 1'b0;
reg b;
reg c;
always@(posedge clk)
begin
a <= 1'b01;
end
always@(posedge clk)
begin
b = a;
end
always@(posedge clk)
begin
c <= a;
end
-snip-

Thank you Dwayne, that is a clear good description to my question. A
follow up, would anything be different if the regs were arrays (like
32-bits values)? Can there be a race-condition when synthesized? If
not, why?

 

[Dwayne Dilbeck]

Doesn't matter if they it is reg a, b,c nor reg[8:0] a,b,c. the same
synthesis rules would apply.

Yes, Race conditions can and WILL happen in synthesis if you do not plan
carefully.

If by race-condition, you mean is there a way for the new value of A jumping
the pipeline and ending up in C and B.

Datain=>A=>B
=>C=>Dataout;

The quick answer is no. Even though you do not have any delay between the
assignment of the flop and when the edge happened. There is a delta delay in
herent in the simulator. Such that all the activities that happen on clk
edge are calculated first then they are applied. When you synthesize the
flip flops are created and you now have the delay inside the flip flop so
once again there will be no skipping the pipeline stage.


"spartan3wiz" <magnus.wedmark@gmail.com> wrote in message
news:46e88323-c2f2-4acb-83a3-61311be4edd2@e10g2000prf.googlegroups.com...

On 14 Jan, 20:20, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote:
Not every synthesis tool will synthesize a default value for "reg a =
1'b0;".

As a result the synthesis is not garanteed to execute the same way that
simulation would. In simulation:

time #clk_cycle A B C
0 0 0 X X
X 1 1 0 0
X 2 1 1 1

I know of atleast one synthesis tool that would ignore the initial value,
it
would then decide that the CLK is not needed, the final synthesized
result
would not have any FF's just assign statements.

ie: assign A =1'b1;
assign B = A;
assign C = A;

That same synthesis tool can be told to keep all flip flops. In that
case
the result would be

time #clk_cycle A B C
0 0 X X X
X 1 1 X X
X 2 1 1 1

"spartan3wiz" <magnus.wedm...@gmail.com> wrote in message

news:8de874fc-382b-4792-8b4b-7a587df13ecc@d4g2000prg.googlegroups.com...

All verilog-experts can you help me with the following example? I'm a
happy hobbyist trying to grasp the most elemental part of verilog.
help me out! Has the code below a clear sense of flow, thus, is it
possible to say exactly what is going to happen in simulation? Is it
safe for Synthesizing into any technology? Is it safe for FPGAs? What
is the value after the first clock cycle,second clock cycle? Please
help me out..

-snip-
reg a = 1'b0;
reg b;
reg c;
always@(posedge clk)
begin
a <= 1'b01;
end
always@(posedge clk)
begin
b = a;
end
always@(posedge clk)
begin
c <= a;
end
-snip-

Thank you Dwayne, that is a clear good description to my question. A
follow up, would anything be different if the regs were arrays (like
32-bits values)? Can there be a race-condition when synthesized? If
not, why?

 

[spartan3wiz]

On Jan 15, 6:48 am, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote:

a,b,c. the same
synthesis rules would apply.

Yes, Race conditions can and WILL happen in synthesis if you do not plan
carefully.

If by race-condition, you mean is there a way for the new value of A jumping
the pipeline and ending up in C and B.

Datain=>A=>B
=>C=>Dataout;

The quick answer is no. Even though you do not have any delay between the
assignment of the flop and when the edge happened. There is a delta delay in
herent in the simulator. Such that all the activities that happen on clk
edge are calculated first then they are applied. When you synthesize the
flip flops are created and you now have the delay inside the flip flop so
once again there will be no skipping the pipeline stage.

"spartan3wiz" <magnus.wedm...@gmail.com> wrote in message

news:46e88323-c2f2-4acb-83a3-61311be4edd2@e10g2000prf.googlegroups.com...

On 14 Jan, 20:20, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote:
Not every synthesis tool will synthesize a default value for "reg a =
1'b0;".

As a result the synthesis is not garanteed to execute the same way that
simulation would. In simulation:

time #clk_cycle A B C
0 0 0 X X
X 1 1 0 0
X 2 1 1 1

I know of atleast one synthesis tool that would ignore the initial value,
it
would then decide that the CLK is not needed, the final synthesized
result
would not have any FF's just assign statements.

ie: assign A =1'b1;
assign B = A;
assign C = A;

That same synthesis tool can be told to keep all flip flops. In that
case
the result would be

time #clk_cycle A B C
0 0 X X X
X 1 1 X X
X 2 1 1 1

"spartan3wiz" <magnus.wedm...@gmail.com> wrote in message

news:8de874fc-382b-4792-8b4b-7a587df13ecc@d4g2000prg.googlegroups.com...

All verilog-experts can you help me with the following example? I'm a
happy hobbyist trying to grasp the most elemental part of verilog.
help me out! Has the code below a clear sense of flow, thus, is it
possible to say exactly what is going to happen in simulation? Is it
safe for Synthesizing into any technology? Is it safe for FPGAs? What
is the value after the first clock cycle,second clock cycle? Please
help me out..

-snip-
reg a = 1'b0;
reg b;
reg c;
always@(posedge clk)
begin
a <= 1'b01;
end
always@(posedge clk)
begin
b = a;
end
always@(posedge clk)
begin
c <= a;
end
-snip-

Thank you Dwayne, that is a clear good description to my question. A
follow up, would anything be different if the regs were arrays (like
32-bits values)? Can there be a race-condition when synthesized? If
not, why?

Thank you again! I now think I fully understand this.

 

[Andreas Ehliar]

On 2008-01-13, spartan3wiz <magnus.wedmark@gmail.com> wrote:

always@(posedge clk)
begin
b = a;
end

Assuming b = a isn't a simple typo on your side:
---------------------------------------------------------
Since you use a blocking assignment here you will most
likely get some problems later on. Look at for example
http://www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblocking_assigns.pdf
for a detailed explanation. (This is something which
all Verilog designers should try to understand.)

Anyway, as a rule of thumb:

Use blocking assignments (e.g. b = a in combinational
blocks. (always @*) (Using non-blocking here is probably
going to work though.)

Use non-blocking assignments (e.g. b <= a in synchronous
blocks. (always @(posedge ...)). (Using blocking assignments
here is probably going to be catastrophic.)

There are some places where it makes sense to break this
guideline, but you shouldn't do that without understanding
the consequences.


If b = a is a typo:
---------------------------------------------------------
Well, perhaps someone else will learn something from the
PDF file mentioned above instead

/Andreas

 

[Mike Treseler]

spartan3wiz wrote:

All verilog-experts can you help me with the following example? I'm a
happy hobbyist trying to grasp the most elemental part of verilog.
help me out! Has the code below a clear sense of flow, thus, is it
possible to say exactly what is going to happen in simulation?

Only for a very simple example
That's why I use a simulator.

Is it
safe for Synthesizing into any technology? Is it safe for FPGAs? What
is the value after the first clock cycle,second clock cycle? Please
help me out..

The safest and most portable
structure is a synchronous block.
Get a simulator and start with
some known-good examples.
Google a bit.

-- Mike

 

[Mike Treseler]

Andreas Ehliar wrote:

Since you use a blocking assignment here you will most
likely get some problems later on.

Blocking assignments work fine
when restricted to a named synchronous block.
For example:
http://home.comcast.net/~mike_treseler/count_enable.v

Look at for example
http://www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblocking_assigns.pdf
for a detailed explanation. (This is something which
all Verilog designers should try to understand.)

This is a fine paper for beginners.
It is too restrictive for others.
I would be unable to translate my vhdl to verilog
if I followed this advice on blocking assignments
in named synchronous blocks.

-- Mike Treseler

 

On Jan 15, 12:48 am, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote:

If by race-condition, you mean is there a way for the new value of A jumping
the pipeline and ending up in C and B.

Datain=>A=>B
                  =>C=>Dataout;

The quick answer is no.  Even though you do not have any delay between the
assignment of the flop and when the edge happened. There is a delta delay in
herent in the simulator. Such that all the activities that happen on clk
edge are calculated first then they are applied.

If the OP had not used a nonblocking assignment to A, the answer could
have been yes. There is no delta delay inherent in a blocking
assignment. The value of A would have been updated immediately. If
the always block assigning to A was evaluated before the ones
assigning to C and B, then they would have seen the updated value.

It is more typical for the other always blocks reading A to be in
different modules, so that the value passes through a port first.
That involves being scheduled onto a wire, which can add delta-cycle-
like delay. That can also provide enough hold time to make this
work. However, Verilog does not mandate any delta-cycle timing, and
overly aggressive optimization could eliminate that delay. For that
reason, it has become common to recommend the use of nonblocking
assignments to delay the update of the variable until after the other
always blocks on the same clock have run.

  When you synthesize the
flip flops are created and you now have the delay inside the flip flop so
once again there will be no skipping the pipeline stage.

Yes, as long as the clock->output propagation delay is greater than
the required hold time of the next stage flop.

 

[glen herrmannsfeldt]

Andreas Ehliar wrote:

On 2008-01-13, spartan3wiz <magnus.wedmark@gmail.com> wrote:

always@(posedge clk)
begin
b = a;
end

Assuming b = a isn't a simple typo on your side:
---------------------------------------------------------
Since you use a blocking assignment here you will most
likely get some problems later on.

Somehow most of my early verilog used blocking assignment and
I don't remember having any problems with it.

First, I used behavioral verilog only for registers,
with each register in its own module. (Though multiple
instances of those modules.) The rest of the logic
was all in continuous assignment statements.

It seems from the description that separate always blocks
with blocking assignment could be executed, and the changes
stored, in any order. For synthesis presumably separate
always blocks will synthesize separate flip-flops, and
everything will work. I thought that the simulation was
also designed to do that.

All mine now use non-blocking assignment, but even so, I
never code any that change the same variable more than
once in a block, or use a variable after it has changed.
(It helps readability even if the meaning is the same.)

-- glen