Verilog, combinational logic and modules?

[mnentwig]

Hi,

I'm getting some strange results from the simulator that I don't understan
(tried both iverilog and ISim).

The design tries to make a combinational assignment inside a module:

module gate (input [1:0] mux, input [17:0] a, output [17:0] b);
assign b = (mux == 1) ? a : 17'hx;
endmodule

What happens is that "a" never gets through to "b".
A similar line outside a module works.
With some time scale settings, it works also. The simulation is completel
algorithmic, no delays, device models or the like.

Does anybody have an idea, what is going on here? Is this a delta-cycl
problem, am I missing something fundamental here?
Apologies if the answer is obvious, but usually I I stick to the safe pat
of fully synchronous logic in Moore machines...

---------------------------------------
Posted through http://www.FPGARelated.com

 

[glen herrmannsfeldt]

mnentwig <24789@embeddedrelated> wrote:

I'm getting some strange results from the simulator that I don't
understand (tried both iverilog and ISim).

The design tries to make a combinational assignment inside a module:

module gate (input [1:0] mux, input [17:0] a, output [17:0] b);
assign b = (mux == 1) ? a : 17'hx;
endmodule

What happens is that "a" never gets through to "b".
A similar line outside a module works.
With some time scale settings, it works also. The simulation
is completely algorithmic, no delays, device models or the like.

Well, it shouldn't get through to "b" unless mux==2'b01.

Not that it should matter, but why not 18'hx instead of 17'hx?

Try putting some other value, such as 18'x12345 instead, so you
will know that some value is getting through. For synthesis, there
is no use for x state, I suppose some for simulation, but more often
I put in an actual, but unexpected, value.

Does anybody have an idea, what is going on here?
Is this a delta-cycle problem, am I missing something
fundamental here?

I don't see any delta cycle problem here, but it is possible
in the instantiating module. If you get the widths wrong, though,
it could confuse everything. Why is mux two bits?

-- glen

 

[Gabor]

On 1/14/2014 12:50 PM, mnentwig wrote:

Hi,

I'm getting some strange results from the simulator that I don't understand
(tried both iverilog and ISim).

The design tries to make a combinational assignment inside a module:

module gate (input [1:0] mux, input [17:0] a, output [17:0] b);
assign b = (mux == 1) ? a : 17'hx;
endmodule

What happens is that "a" never gets through to "b".
A similar line outside a module works.
With some time scale settings, it works also. The simulation is completely
algorithmic, no delays, device models or the like.

Does anybody have an idea, what is going on here? Is this a delta-cycle
problem, am I missing something fundamental here?
Apologies if the answer is obvious, but usually I I stick to the safe path
of fully synchronous logic in Moore machines...

---------------------------------------
Posted through http://www.FPGARelated.com

Maybe you have a problem with the code that instantiates this module?
Or were you saying that this is all you tried to simulate?
Can you post the test bench code that didn't work?

--
Gabor

 

[mnentwig]

Hi,

well, the example got a bit sloppy, after I edited it about 20 times.
The "17" bit width should be "18", but this works anywhere else (usually
just write 'hx).
The mux control is 2 bit wide because of four states.
The purpose of the block to arbitrate memory access between up to fou
parties. But the output remains undefined for any value of "mux". If I mov
the line out of the module, it works as it should.

I guess it's a simulator glitch. Weird though, the rest of the projec
works exactly as intended, but there all the modules are registered.
Maybe I'll try the original code again in a week, with everything els
cleaned up. It's a only a fun project, no deadline.


---------------------------------------
Posted through http://www.FPGARelated.com

 

[GaborSzakacs]

mnentwig wrote:

Hi,

well, the example got a bit sloppy, after I edited it about 20 times.
The "17" bit width should be "18", but this works anywhere else (usually I
just write 'hx).
The mux control is 2 bit wide because of four states.
The purpose of the block to arbitrate memory access between up to four
parties. But the output remains undefined for any value of "mux". If I move
the line out of the module, it works as it should.

I guess it's a simulator glitch. Weird though, the rest of the project
works exactly as intended, but there all the modules are registered.
Maybe I'll try the original code again in a week, with everything else
cleaned up. It's a only a fun project, no deadline.


---------------------------------------
Posted through http://www.FPGARelated.com

It would be strange for two different simulators to have the same
"glitch." I'm still guessing that the instantiating code has
something odd about it. Can you post the simplest test case
that gives this behavior so I could try it on ModelSim?

--
Gabor