Verilog coding styles for ASICs

[Muruku ANAND]

Hello friends!!
I was wondering if anyone can explain some important coding styles for
ASICs as compared to FPGAs. What are the things which makes a Design
which is more specific to FPGAs easily portable to ASICs.

Thanks in advance.

Muruku

 

[Prasanna]

Hi,

Here are some I can think of...

There is this logic to routing ratio (approx. 40:60)you always keep in
mind while you do FPGAs. By this you estimate how much time you have
for your logic and how many levels that you can code with. It also
depends on FPGA technology what can go into one CLB unit (logical unit
of FPGA -> roughly analogous to a standard cell) and that is where
your coding style comes into picture. FGPA synthesis tools does not
give you a lot of leverage when it comes to fanout issues. Consider
replication and duplication of logic issues. All FPGA designs are not
portable to ASIC and vice-versa). For example : If there are specific
guidelines on protocol regarding latency, response time, arbiteration
issues, datapaths, you will find FPGAs are sometimes too slow for
implementation.

Corrections gracefully accepted.

- Prasanna

Andrew Paule <lsboogy@qwest.net> wrote in message news:<DTXSa.59$ez2.51059@news.uswest.net>...

Hi Muruku:

I guess the easiest way to explain this in a simple manner is that ASICs
can range from standard core types, to standard cell types, to full
custom. If you are an FPGA guy, the thing to realize is that all of the
black box components that you are either intantiating in a file or are
being pulled in by the compiler are what you are either going to have to
get from you ASIC manufacturer (if using a standard cell or core type)
or that you will have to create using available transitor/resitor/(maybe
cap/even less likely inductor) combinations. Either way, to ease
portability, you should not intantiate any black box components in your
designs if you want to port them, and make sure you understand the
design flow and limitations of the target ASIC before commiting to an
FPGA type to start implementation/design verification runs

Andrew.

Muruku ANAND wrote:

Hello friends!!
I was wondering if anyone can explain some important coding styles for
ASICs as compared to FPGAs. What are the things which makes a Design
which is more specific to FPGAs easily portable to ASICs.

Thanks in advance.

Muruku

 

[Muruku ANAND]

Hi Prasanna:
Can you put some more light on these questions.

There is this logic to routing ratio (approx. 40:60)you always keep in
mind while you do FPGAs. By this you estimate how much time you have
for your logic and how many levels that you can code with. It also
depends on FPGA technology what can go into one CLB unit (logical unit
of FPGA -> roughly analogous to a standard cell) and that is where
your coding style comes into picture. FGPA synthesis tools does not

Can you please detail out how or what tools are contexed for the above
situation. I am not quite able to relate logic to routing ratio,
timing and levels of code. What do you mean by levels of code? I have
done some layouts and understand some of the things in cell libraries
and their design issues.
I would appreciate your answers.

give you a lot of leverage when it comes to fanout issues. Consider
replication and duplication of logic issues. All FPGA designs are not
portable to ASIC and vice-versa). For example : If there are specific
guidelines on protocol regarding latency, response time, arbiteration
issues, datapaths, you will find FPGAs are sometimes too slow for
implementation.

I understand these issues perfectly well.
How is ASIC synthesis different from FPGA synthesis?

Thanks
Muruku

 

[Andrew Paule]

ASIC can be either standard or custom cell, or full blown custom.
Standard cell means that there are a number of cell types defined,
usually in a given area of the chipbut you can move them to some extent;
custom cell means that there are generally fields of transistors and
resistors (placement somewhat defined); and full custom means you do all
the masks - your processor is a full custom ASIC. Trying to understand
movement into an ASIC requires knowledge beforehand of the ASIC
structures that you are moving into, unless you are using one of the
firms that transfer your FPGA into a burned silicon part. There be dragons.

Andrew



Muruku ANAND wrote:

Hi Prasanna:
Can you put some more light on these questions.



There is this logic to routing ratio (approx. 40:60)you always keep in
mind while you do FPGAs. By this you estimate how much time you have
for your logic and how many levels that you can code with. It also
depends on FPGA technology what can go into one CLB unit (logical unit
of FPGA -> roughly analogous to a standard cell) and that is where
your coding style comes into picture. FGPA synthesis tools does not



Can you please detail out how or what tools are contexed for the above
situation. I am not quite able to relate logic to routing ratio,
timing and levels of code. What do you mean by levels of code? I have
done some layouts and understand some of the things in cell libraries
and their design issues.
I would appreciate your answers.



give you a lot of leverage when it comes to fanout issues. Consider
replication and duplication of logic issues. All FPGA designs are not
portable to ASIC and vice-versa). For example : If there are specific
guidelines on protocol regarding latency, response time, arbiteration
issues, datapaths, you will find FPGAs are sometimes too slow for
implementation.



I understand these issues perfectly well.
How is ASIC synthesis different from FPGA synthesis?

Thanks
Muruku

 

[Prasanna]

Andrew Paule <lsboogy@qwest.net> wrote in message news:<zvITa.108$RO2.163415@news.uswest.net>...

ASIC can be either standard or custom cell, or full blown custom.
Standard cell means that there are a number of cell types defined,
usually in a given area of the chipbut you can move them to some extent;
custom cell means that there are generally fields of transistors and
resistors (placement somewhat defined); and full custom means you do all
the masks - your processor is a full custom ASIC. Trying to understand
movement into an ASIC requires knowledge beforehand of the ASIC
structures that you are moving into, unless you are using one of the
firms that transfer your FPGA into a burned silicon part. There be dragons.

Andrew



Muruku ANAND wrote:

Hi Prasanna:
Can you put some more light on these questions.



There is this logic to routing ratio (approx. 40:60)you always keep in
mind while you do FPGAs. By this you estimate how much time you have
for your logic and how many levels that you can code with. It also
depends on FPGA technology what can go into one CLB unit (logical unit
of FPGA -> roughly analogous to a standard cell) and that is where
your coding style comes into picture. FGPA synthesis tools does not



Can you please detail out how or what tools are contexed for the above
situation. I am not quite able to relate logic to routing ratio,
timing and levels of code. What do you mean by levels of code? I have
done some layouts and understand some of the things in cell libraries
and their design issues.
I would appreciate your answers.



give you a lot of leverage when it comes to fanout issues. Consider
replication and duplication of logic issues. All FPGA designs are not
portable to ASIC and vice-versa). For example : If there are specific
guidelines on protocol regarding latency, response time, arbiteration
issues, datapaths, you will find FPGAs are sometimes too slow for
implementation.



I understand these issues perfectly well.
How is ASIC synthesis different from FPGA synthesis?

Thanks
Muruku

Hello Muruku,

Sorry for the delay in reply. I just read your email now. There are 2
delays which you consider for timing. The gate delays and the
interconnect delays. The gate delays (logic) and the interconnect
(routing) are comparable in deep sub-micron technologies and can give
you surprises. There are both good and bad things about this in ASIC
and FPGAs. While FPGAs interconnects are somewhat predictable and
pre-determined, the ASICs (by your standard cell design knowledge),
you know that there are wireload models included by statistical method
which are not quite accurate for deep sub-micron. Due to this,
synopsys has developed PKS which effectively means that you know where
your logic blocks sit so that your interconnect delays are much more
predictable and you are bound for less surprises when you do the
backend for your logic. The number of levels of logic is the term used
to define how many blocks of combinatorial logic you put between 2
flops (registers). This is a very rough term bcoz' an adder will not
have the same delay as a nand gate. However, while you code, you
ensure some things such as,

1. comparing 2 variables against comparing a variable with a static
value.
2. Coding with higher abstract level against coding at lower abstract
level (to infer the standard cell that you know exists in the cell
library).

Regarding synthesis,

ASIC synthesis seems to be a ocean (with lot of insight and handles)
and FPGA synthesis seems to be a well. While most FPGA synthesis job
seems like a push button job, since each FPGA vendor comes up with his
own set of EDA tools, experiences differ. Some FPGA synthesis tools
dont offer maximum fanout control while some do, some replicates logic
unneccessarily, while some synthesise better if you change order of
files (bugs !!!), some do insert lot of buffers. Some FPGA synthesis
tools provide option to take care of critical path first (after you
find the worst slack). There are other issues related to multi-clock
domains and I/O timing issues which is a seperate topic by itself.

For asic synthesis, go thru' Synopsys DC manual and you get all the
information that you need.

Hope that helps.

Good luck...