Verilog coding question

[ndesi]

Hello,

In my design i have big counter and i have to do different thing
at different count value.

If i implement like this:
--------------------------------------------------
always @ (posedge clk or negedge rst_n) begin
if (~rst_n) begin
item1 <= 0;
item2 <= 0;
.
.
.
end
else if (count == value1)
item1 <= 1;
else if (count == value2)
item1 <= 2;
else if (count == more values)
more signal
end
--------------------------------------------------
For lot of counter decode value it is not easily readable

any other way i can implement this??

Thanks

 

[Peng Cong]

case(count)
value1:item1 <= 1;
value2:item1 <= 2;
....
default:...
endcase

"ndesi" <ndesi@talk21.com> Đ´ČëÓĘźţ
news:cf531019.0405111736.368f8133@posting.google.com...

Hello,

In my design i have big counter and i have to do different thing
at different count value.

If i implement like this:
--------------------------------------------------
always @ (posedge clk or negedge rst_n) begin
if (~rst_n) begin
item1 <= 0;
item2 <= 0;
.
.
.
end
else if (count == value1)
item1 <= 1;
else if (count == value2)
item1 <= 2;
else if (count == more values)
more signal
end
--------------------------------------------------
For lot of counter decode value it is not easily readable

any other way i can implement this??

Thanks