verilog code

hi,how to generate verilog code for a delay(z^-1)and for down
sampling of 2?

 

[Andreas Ehliar]

On 2008-10-31, aparna_sankar6@yahoo.co.in <aparna_sankar6@yahoo.co.in> wrote:

hi,how to generate verilog code for a delay(z^-1)and for down
sampling of 2?

This sounds suspiciously like a homework exercise. If so I guess your professor
would be very interested in knowing that you are asking these kind of questions
on Usenet.


Anyway, just as a hint towards the answer:

If you assume that you have a clock which is running at your sample frequency
this should be extremely easy to do.

/Andreas