Verilog code to Physical layout?

[KaRtiK]

Is there some way I can generate a physical layout (using Cadence) of
a design written in Verilog and synthesized using Synopsys design
compiler.
I heard there was provision in Cadence for this..
Any one tried this before?

 

[Rudolf Usselmann]

kkrishnan@wisc.edu (KaRtiK) wrote in message news:<11510c1b.0401292116.28e83545@posting.google.com>...

Is there some way I can generate a physical layout (using Cadence) of
a design written in Verilog and synthesized using Synopsys design
compiler.
I heard there was provision in Cadence for this..
Any one tried this before?

Yes, Cadence provides tools for th entire full
custom/std. cell chip design flow.

But I'll bet neither one of us (as an individual)can
afford them !

Also look at Magma, they have a single tool solution ...

Cheers,
rudi
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