verilog code reading problem

[anupam]

Hi All,
I am trying to read this verilog code.
Can u tell me that what is meant for ENA and ENB ?
Regards,
Thanx in advance.

CODE--------
assign mpi_data_out = (mpi_cs & ~mpi_addr[8]) ? mpi_mem_bus_out[8:0] :
(mpi_cs & mpi_addr[8]) ? {7'h00, ctrl_out} :
9'hzzz;

assign mpi_mem_bus_in = {{7{pd}}, mpi_data_in};
assign ram_en = mpi_cs & ~mpi_addr[8];

RAMB4_S16_S16 c_mem (
.DOA (cd_data),
.DOB (mpi_mem_bus_out),
.ADDRA (c_mem_addr),
.ADDRB (mpi_addr[7:0]),
.CLKA (clk_4096k),
.CLKB (mpi_clk),
.DIA ({16{pd}}),
.DIB (mpi_mem_bus_in),
.ENA (cd_en),
.ENB (ram_en),
.RSTA (~g_rst),
.RSTB (~g_rst),
.WEA (pd),
.WEB (~mpi_rw)
);

 

[Uwe Bonnes]

anupam <anupam@coraltele.com> wrote:
: Hi All,
: I am trying to read this verilog code.
: Can u tell me that what is meant for ENA and ENB ?
: Regards,
: Thanx in advance.

: CODE--------
: assign mpi_data_out = (mpi_cs & ~mpi_addr[8]) ? mpi_mem_bus_out[8:0] :
: (mpi_cs & mpi_addr[8]) ? {7'h00, ctrl_out} :
: 9'hzzz;
:
: assign mpi_mem_bus_in = {{7{pd}}, mpi_data_in};
: assign ram_en = mpi_cs & ~mpi_addr[8];

: RAMB4_S16_S16 c_mem (

Look on the XILINX Site for an explication for the RAM block.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
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