Verilog - Code Posted - Please Help !!

[dash82]

Hi Everyone,

I am new to Verilog. I am trying to code a 1/2 rate convolutional
encoder (http://en.wikipedia.org/wiki/Convolutional_code) in Verilog.
I have the written the code and the test bench for it.

However, i am going wrong somewhere. Anyone's help would be greatly
appreciated.

Verilog code:

//1/2 rate convolutional code with 3 registers; polynomials being
(1,1,1) & //(1,0,1)

module omencoder(out1,out2,in1,clk);


output out1, out2;
input in1,clk;


reg u0 = 1'b0 ,u1 = 1'b0 ,u2 = 1'b0 , temp_u0, temp_u1, temp_u2;


always @(in1)

begin

temp_u0 <= u0;
temp_u1 <= u1;
temp_u2 <= u2;

//I was facing a race condition. Hence tried to put delay statement.
#2 assign u2 = temp_u1;
$display("value of u2 = %b",u2);
#4 assign u1 = temp_u0;
$display("value of u1 = %b",u1);
#6 assign u0 = in1;
$display("value of u0 = %b",u0);

end

//using polynomials (1,1,1) & (1,0,1)

xor (out1,u0,u1,u2);
xor (out2,u0,u2);

endmodule


----------------------------------

Testbench:

--------------------------------------
module stimulus;
reg clk;
reg in1 = 1'b1;


omencoder om1(out1,out2,in1,clk);

initial
begin

clk = 1'b1;


#50 in1= 1'b1;
#100 in1= 1'b0;
#150 in1= 1'b1;
#200 in1= 1'b0;
//the last 2 input bits are used to flush the registers.
#250 in1= 1'b0;
#300 in1= 1'b0;
#350 $finish;
end

initial
$monitor("output bit 1 = %b, output bit 2 = %b", out1,out2);

endmodule

-----------------------------------------------------------------

 

[gabor]

Wow!

Where to start?

Is this code, omencoder not the testbench, supposed to be
synthesizable?

1) you have a clock signal coming into your module. I would
suggest using this instead of looking for changes in in1.

2) if your code needs to be synthesizable, forget the # delays and
use non-blocking assignments in a clocked block using clk:

always @ (posedge clk)
begin
out1 <= ...
out2 <= ...
end

or better add a reset term so you have a chance of simulating the
design like:

always @ (posedge clk or posedge reset)
if (reset)
begin
out1 <= 0;
out2 <= 0;
end
else
begin
out1 <= ...
out2 <= ...
end

3) perhaps this should be point 1, read a Verilog book like
Thomas & Moorby's "The Verilog Hardware Description Language"
or some other book of your choice.

Have fun,

Gabor

On Oct 23, 4:08 am, dash82 <dhavalru...@gmail.com> wrote:

Hi Everyone,

I am new to Verilog. I am trying to code a 1/2 rate convolutional
encoder (http://en.wikipedia.org/wiki/Convolutional_code) in Verilog.
I have the written the code and the test bench for it.

However, i am going wrong somewhere. Anyone's help would be greatly
appreciated.

Verilog code:

//1/2 rate convolutional code with 3 registers; polynomials being
(1,1,1) & //(1,0,1)

module omencoder(out1,out2,in1,clk);

output out1, out2;
input in1,clk;

reg u0 = 1'b0 ,u1 = 1'b0 ,u2 = 1'b0 , temp_u0, temp_u1, temp_u2;

always @(in1)

begin

temp_u0 <= u0;
temp_u1 <= u1;
temp_u2 <= u2;

//I was facing a race condition. Hence tried to put delay statement.
#2 assign u2 = temp_u1;
$display("value of u2 = %b",u2);
#4 assign u1 = temp_u0;
$display("value of u1 = %b",u1);
#6 assign u0 = in1;
$display("value of u0 = %b",u0);

end

//using polynomials (1,1,1) & (1,0,1)

xor (out1,u0,u1,u2);
xor (out2,u0,u2);

endmodule

----------------------------------

Testbench:

--------------------------------------
module stimulus;
reg clk;
reg in1 = 1'b1;

omencoder om1(out1,out2,in1,clk);

initial
begin

clk = 1'b1;

#50 in1= 1'b1;
#100 in1= 1'b0;
#150 in1= 1'b1;
#200 in1= 1'b0;
//the last 2 input bits are used to flush the registers.
#250 in1= 1'b0;
#300 in1= 1'b0;
#350 $finish;
end

initial
$monitor("output bit 1 = %b, output bit 2 = %b", out1,out2);

endmodule

-----------------------------------------------------------------