Apr 22, 2022 #1 K KRISHNA CHAITHANYA Guest Kindly suggest or provide the Verilog code parallel CRC generation using LFSR and using polynomial for 256-bit data with a 32-bit polynomial.
Kindly suggest or provide the Verilog code parallel CRC generation using LFSR and using polynomial for 256-bit data with a 32-bit polynomial.
May 1, 2022 #2 H Hariprasad Bhat Guest On Friday, April 22, 2022 at 4:17:59 PM UTC+5:30, chait...@gmail.com wrote: Kindly suggest or provide the Verilog code parallel CRC generation using LFSR and using polynomial for 256-bit data with a 32-bit polynomial. Hi, Click to expand... Kindly Refer to below link. https://www.researchgate.net/publication/283294945_Concurrent_Generation_of_Pseudo_Random_Numbers_with_LFSR_of_Fibonacci_and_Galois_Type With this you can implement your requirements. I have implemented 64-bit & 128 bit scrambler using attached paper & it is working fine. With Regards, HP Bhat
On Friday, April 22, 2022 at 4:17:59 PM UTC+5:30, chait...@gmail.com wrote: Kindly suggest or provide the Verilog code parallel CRC generation using LFSR and using polynomial for 256-bit data with a 32-bit polynomial. Hi, Click to expand... Kindly Refer to below link. https://www.researchgate.net/publication/283294945_Concurrent_Generation_of_Pseudo_Random_Numbers_with_LFSR_of_Fibonacci_and_Galois_Type With this you can implement your requirements. I have implemented 64-bit & 128 bit scrambler using attached paper & it is working fine. With Regards, HP Bhat
