verilog code error

[khushalgelda]

// this is a code to learn how to take input from ps2 keyboard..


module ps2(clock,x,y);
input x;
input clock;
output reg [7:0] y;
integer i;
always @(negedge clock)
begin
if (~x)
begin
i=0;
repeat (10)
begin
@(negedge clock) y = x;
i=i+1;
end
end
end
endmodule


error that is ocurring is : "Unsupported Event Control Statement. "..
plz reply wats the problem in my code

 

[Cary R.]

On 9/28/2010 6:31 AM, khushalgelda wrote:

error that is ocurring is : "Unsupported Event Control Statement. "..
plz reply wats the problem in my code

Surely the simulator is also giving you a line number. Why make us guess
where the problem is? This code snippet compiles just fine using GPLcver
and Icarus. At first glance the event controls look correct.

Cary

 

[Andy]

On Sep 28, 10:58 am, "Cary R." <no-s...@host.spam> wrote:

On 9/28/2010 6:31 AM, khushalgelda wrote:

error that is ocurring is : "Unsupported Event Control Statement. "..
plz reply wats the problem in my code

Surely the simulator is also giving you a line number. Why make us guess
where the problem is? This code snippet compiles just fine using GPLcver
and Icarus. At first glance the event controls look correct.

Cary

I'm betting he's using a synthesis tool. But stating such (i.e. which
one) and including the line number would be helpful.

andy

 

[Muzaffer Kal]

On Tue, 28 Sep 2010 06:31:05 -0700 (PDT), khushalgelda
<khushalgelda@gmail.com> wrote:

// this is a code to learn how to take input from ps2 keyboard..


module ps2(clock,x,y);
input x;
input clock;
output reg [7:0] y;
integer i;
always @(negedge clock)
begin
if (~x)
begin
i=0;
repeat (10)
begin
@(negedge clock) y = x;
i=i+1;
end
end
end
endmodule


error that is ocurring is : "Unsupported Event Control Statement. "..
plz reply wats the problem in my code

Your problem is with the line with extra '>'s. Most synthesis tools
don't support this type of event which implements an implicit state
machine. You need to figure out how to get rid of the @(..) in that
line and use only 'x' as your control signal from which you need to
start counting and reading.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

 

[gabor]

On Sep 28, 3:47 pm, Muzaffer Kal <k...@dspia.com> wrote:

On Tue, 28 Sep 2010 06:31:05 -0700 (PDT), khushalgelda



khushalge...@gmail.com> wrote:
// this is a code to learn how to take input from ps2 keyboard..

module ps2(clock,x,y);
input x;
input clock;
output reg [7:0] y;
integer i;
always @(negedge clock)
   begin
           if (~x)
           begin
            i=0;
             repeat (10)
             begin
                               @(negedge clock) y = x;
                           i=i+1;
                   end
           end
   end
endmodule

error that is ocurring is : "Unsupported Event Control Statement. "..
plz reply wats the problem in my code

Your problem is with the line with extra '>'s. Most synthesis tools
don't support this type of event which implements an implicit state
machine. You need to figure out how to get rid of the @(..) in that
line and use only 'x' as your control signal from which you need to
start counting and reading.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Synthesis tools also generally don't allow the repeat operator
or @ (negedge clock) inside a procedural block except at the
top of an always block. If this needs to be synthesized you
need to find a good reference on synthesizable Verilog.

Regards,
Gabor