Verilog code conversion to scheme (graphical). Newbie.

A

Actarus

Guest
Hi all,
I start coding Verilog last week (my company decide to move me to FPGA
design group).
I've to continue a work started by a colleague that has left the
company one month ago.
Ex-colleague is not reachable and he don't write any docs about the
code...I'm going crazy...

I'm asking if there's a tool (win or linux) that generate a
comprehensive schematic from a lot of .v files...
Someone could help me?

Thanks in advance, best regards to all,
Act@rus.
 
Actarus wrote:

I start coding Verilog last week (my company decide to move me to FPGA
design group).
I've to continue a work started by a colleague that has left the
company one month ago.
Ex-colleague is not reachable and he don't write any docs about the
code...I'm going crazy...
Click to expand...
I would start from scratch.
Your ex-colleague would have finished
the work if he knew what he was doing.

I'm asking if there's a tool (win or linux) that generate a
comprehensive schematic from a lot of .v files...
Someone could help me?
Click to expand...
I use Quartus rtl viewer for that.

-- Mike Treseler
 
You're in the FPGA group now.
Are you targeting an FPGA with your code?
Are you using a Synplicity synthesizer? Xilinx? Altera?


"Actarus" <bubugian@gmail.com> wrote in message
news:1177496466.732811.192900@r3g2000prh.googlegroups.com...
Hi all,
I start coding Verilog last week (my company decide to move me to FPGA
design group).
I've to continue a work started by a colleague that has left the
company one month ago.
Ex-colleague is not reachable and he don't write any docs about the
code...I'm going crazy...

I'm asking if there's a tool (win or linux) that generate a
comprehensive schematic from a lot of .v files...
Someone could help me?

Thanks in advance, best regards to all,
Act@rus.
Click to expand...
 
John_H ha scritto:
Are you using a Synplicity synthesizer? Xilinx? Altera?
I'm using ISE 7.1 + Synplicity with a spartan 3 FPGA.
Click to expand...

I've tried 'view RTL schematics' with a ise project.
Now, I'm trying to generate a schematics from a top.v that include
several other .v without having them inside a ise project...

Thanks for your help.
Act@rus
 
On Apr 27, 2:43 am, Actarus <bubug...@gmail.com> wrote:
John_H ha scritto:> Are you using a Synplicity synthesizer? Xilinx? Altera?

I'm using ISE 7.1 + Synplicity with a spartan 3 FPGA.

I've tried 'view RTL schematics' with a ise project.
Now, I'm trying to generate a schematics from a top.v that include
several other .v without having them inside a ise project...

Thanks for your help.
Act@rus
Click to expand...
If the various files are not "in a project", how is the tool to know
how they are related?

If you have Symplify Pro, it includes an RTL viewer which is better
IMHO than the one in ISE.

But no matter what you use, you're going to have to tell the tool
which files you want to use (by adding them to the project).

Andy
 
Andy wrote:
On Apr 27, 2:43 am, Actarus <bubug...@gmail.com> wrote:
John_H ha scritto:> Are you using a Synplicity synthesizer? Xilinx? Altera?

I'm using ISE 7.1 + Synplicity with a spartan 3 FPGA.

I've tried 'view RTL schematics' with a ise project.
Now, I'm trying to generate a schematics from a top.v that include
several other .v without having them inside a ise project...

Thanks for your help.
Act@rus

If the various files are not "in a project", how is the tool to know
how they are related?

If you have Symplify Pro, it includes an RTL viewer which is better
IMHO than the one in ISE.

But no matter what you use, you're going to have to tell the tool
which files you want to use (by adding them to the project).

Andy
Click to expand...
Specifically, the Synplicity tool is HDL Analyst which is bundled in
free with SynplifyPro but is available for Synplify.

I highly recommend HDL Analyst for visualization of your design,
particularly when trying to meet timing with the "critical path"
highlighted for you in the technology viewer.

For general understanding of a design, the RTL viewer would be the way
to go.

I'm amazed at the number of people who have this tool available to them
and don't bother to find out what it can do for them. In my opinion,
this is one of the most powerful tools available to the designer for
optimization and timing closure. PLEASE, if you use Synplicity tools,
look into it!

- John_H
 
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