Verilog Binary Division

[Kristo Godari]

I need a Verilog behavioral model (verilog behavioral code) for:
- unsigned 8-bit division

The module I have to use is this one:

module divider(
output reg[7:0] q,
output reg[7:0] r,
input [7:0] a,b);
endmodule

where a=b*q+r

Is preferable to use SRT, Newton-Raphson or Goldschmidt algorithms
to solve it.

Can someone help me?

 

[Mark Curry]

In article <2e94162d-8244-4c18-b91c-5d4f07c009d2@googlegroups.com>,
Kristo Godari <kristo.godari@gmail.com> wrote:

I need a Verilog behavioral model (verilog behavioral code) for:
- unsigned 8-bit division

How's this?

module divider(
output wire[7:0] q,
output wire[7:0] r,
input wire [7:0] a,b);

assign q = b / a;
assign r = b % a;

endmodule

You've probably left out details on why the simple solution doesn't work...

Regards,

Mark

 

[Kristo Godari]

Thank you Mark but i forgot to say that i can't use '/' or '%'!

 

[Nikolaos Kavvadias]

Hi Kristo,

I can even use Babylonian algorithms if this could suit you.

SRT, Goldschmidt, and NR are all within my reach.

Best regards
Nikolaos Kavvadias