Verilog attribute on declaration of multiple registers on th

[Jim Wu]

Below is an example from the LRM. It kind of implies that both state2
and state3 will have an attribute fsm_state=1. However, I can't find a
definitive and explicit statement in the LRM to confirm that is the
case. Any comments?

(* fsm_state=1 *) reg [3:0] state2, state3;

Cheers,
Jim

 

On Jun 10, 4:50 pm, Jim Wu <jimwu88NOOOS...@yahoo.com> wrote:

Below is an example from the LRM. It kind of implies  that both state2
and state3 will have an attribute fsm_state=1. However, I can't find a
definitive and explicit statement in the LRM to confirm that is the
case. Any comments?

(* fsm_state=1 *) reg [3:0] state2, state3;

That is the intent. If you don't want the attribute attached to one
of the variables, then you will have to declare them in separate
declarations.