Verilog ASIC conversion to Xilinx FPGA - GOTCHA

[Chris Smoot]

Hi all,

Something that may be of interest when converting Verilog ASIC designs
to Xilinx FPGAs. I noticed this when trying to convert a customer's
ASIC design. When trying to set a clock to out constraint on an
output that is being driven by an inout (see sample below), the place
and route tool ignores the constraint, and gives the following msg:

WARNING:Timing:2667 - CLK does not clock data to metoo
WARNING:Timing:2666 - Constraint ignored: TIMEGRP "metoo" OFFSET = OUT
10 nS AFTER COMP "CLK" ;


//EXAMPLE CODE
module test (CLK, RST, ENABLE, IN, BIDIR, METOO);
input CLK, RST, ENABLE, IN;
inout BIDIR;
output METOO;

reg test_reg;

always @(posedge CLK or posedge RST)
if (RST)
test_reg <= 1'b0;
else
test_reg <= IN;

assign BIDIR = ENABLE ? test_reg : 1'bz;
assign METOO = BIDIR;

endmodule


I was able to get around it by making the following easy change.


//MODIFIED EXAMPLE
module test (CLK, RST, ENABLE, IN, BIDIR, METOO);
input CLK, RST, ENABLE, IN;
inout BIDIR;
output METOO;

reg test_reg;

always @(posedge CLK or posedge RST)
if (RST)
test_reg <= 1'b0;
else
test_reg <= IN;

assign BIDIR = ENABLE ? test_reg : 1'bz;
assign METOO = ENABLE ? test_reg : BIDIR;

endmodule

With all the constraints being checked, I was able to move on to some
"real" problems.