verilog and timing closure

[Johann Klammer]

Is there some sekrit program that reads two vcd files, with min and max delays in each one,
and outputs a third file which has X in those bits that differ in the two input files.

.... or how do 'real experts' verify timing...?

 

[Mark Curry]

In article <mh8ts4$20p$1@speranza.aioe.org>,
Johann Klammer <klammerj@NOSPAM.a1.net> wrote:

Is there some sekrit program that reads two vcd files, with min and max delays in each one,
and outputs a third file which has X in those bits that differ in the two input files.

... or how do 'real experts' verify timing...?

We verify timing with Static Timing Analysis.

Gate level sims with timing are so 1990s. Even then, it was fading fast -
By mid-1990s, gone, except under extremely limited circumstances.

I know of no such tool. I recall VCD parsers out there in Perl or other
languages. It's not a complicated parse. You could write one yourself.

Nah - to troublesome. You'd need to correlate edges, and other hijinks I think.
Just wouldn't work easily once you started fleshing out the details.

--Mark

 

[Johann Klammer]

Finally cobbled sthg together...

<https://github.com/klammerj/vcdmerge>

 

[michael6866]

On Wednesday, June 17, 2015 at 8:38:03 AM UTC-4, Johann Klammer wrote:

Finally cobbled sthg together...

https://github.com/klammerj/vcdmerge

Good work. Or if you only want to find out differences then you can use Simvision's quick diff:

http://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/02/06/heading-off-the-butterfly-effect-the-simvision-quot-quick-diff-quot