VERILOG and SAIF

[abhishek]

SAIF is switching activity interchange format.This feature is used by
synthesis tools for power optimisation.As far as my understanding goes,
SAIF is senstive only to value changes of the registers or wire.
Whenever there is a transition b/w four logic states 0,1,X,Z , it
calculates the power used in these transitions.

However if there is no value change on a reg/wire, but there is a
change of voltage only (strength of that particular wire/reg changes)
then does this bvoltage chane also leads to power consumption.
And if yes then it should also be voltage chjanges(when value is
constant) should also be recorded by our synthesis tool) for power
optimisation.
Please respond asap.


Thanks
Abhishek

 

[Swapnajit Mittra]

One also wonders why people use CMOS logic so extensively
compared to other types.

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