verilog and runtime directive around continuous assignment

[sense]

Hi all,

I have a continuous assingment in verilog which I want to exclude in a
simulation under certain condition. Having a `ifdef `endif around the
code requires me to recompile and I cannot have a testplusarg around a
continuous assignment.

Any way to work around this problem?

Sagar

 

[glen herrmannsfeldt]

sense <sagar.1986@gmail.com> wrote:

I have a continuous assingment in verilog which I want to exclude in a
simulation under certain condition. Having a `ifdef `endif around the
code requires me to recompile and I cannot have a testplusarg around a
continuous assignment.

What do you want it to be when it isn't assigned?

Any way to work around this problem?

How about

assign x = (condition) ? value : 8'hz;

That is, tristate based on condition. Though zero might
be a better choice.

-- glen