verilog and RTL for ~0

[RolfK]

Dear Experts,

I have a simple question.
In verilog (2001) I use:

vector[WITH:0] = ~0 ;

to set all bits of a vector to 1.

This works fine in verilog for my RTL simulation.
But can I be sure that all nice syntheis and formal verifier tools
from big vendors like Synopsys and Cadence do understand this well ?
Does anybody have successfully used in some project ?

Thanks a lot for your feedback

Rolf

 

[Jim Wu]

On Dec 9, 12:03 pm, RolfK <Rolf.Kem...@renesas.com> wrote:

Dear Experts,

I have a simple question.
In verilog (2001) I use:

 vector[WITH:0] = ~0 ;

to set all bits of a vector to 1.

This works fine in verilog for my RTL simulation.
But can I be sure that all nice syntheis and formal verifier tools
from big vendors like Synopsys and Cadence do understand this well ?
Does anybody have successfully used in some project ?

Thanks a lot for your feedback

Rolf

Unsized numbers are extended to 32-bit per Verilog LRM, so your code
only works if WITH <= 31. A better approach for what you're trying to
would be using concatenation operator vector[WITH:0] = {(WITH+1)
{1'b1}};, which works for all WITH values.

Cheers,
Jim
http://myfpgablog.blogspot.com/

 

[Cary R.]

On 12/12/2011 8:53 PM, Jim Wu wrote:

On Dec 9, 12:03 pm, RolfK<Rolf.Kem...@renesas.com> wrote:
Dear Experts,

I have a simple question.
In verilog (2001) I use:

vector[WITH:0] = ~0 ;

to set all bits of a vector to 1.

This works fine in verilog for my RTL simulation.
But can I be sure that all nice syntheis and formal verifier tools
from big vendors like Synopsys and Cadence do understand this well ?
Does anybody have successfully used in some project ?

Thanks a lot for your feedback

Rolf

Unsized numbers are extended to 32-bit per Verilog LRM, so your code
only works if WITH<= 31. A better approach for what you're trying to
would be using concatenation operator vector[WITH:0] = {(WITH+1)
{1'b1}};, which works for all WITH values.

Cheers,
Jim
http://myfpgablog.blogspot.com/

This is only part of what the standard says!

Yes simple decimal numbers are extended to integer width which must be
at least 32 bits, but you skipped the expression sizing rules where the
signed integer value will be sign extended to the larger of the R-value
or L-value width. It is then processed by the ~ operator which produces
a value that will always fill the vector with all 1 bits.

Cary

 

[Gabor]

Cary R. wrote:

On 12/12/2011 8:53 PM, Jim Wu wrote:
On Dec 9, 12:03 pm, RolfK<Rolf.Kem...@renesas.com> wrote:
Dear Experts,

I have a simple question.
In verilog (2001) I use:

vector[WITH:0] = ~0 ;

to set all bits of a vector to 1.

This works fine in verilog for my RTL simulation.
But can I be sure that all nice syntheis and formal verifier tools
from big vendors like Synopsys and Cadence do understand this well ?
Does anybody have successfully used in some project ?

Thanks a lot for your feedback

Rolf

Unsized numbers are extended to 32-bit per Verilog LRM, so your code
only works if WITH<= 31. A better approach for what you're trying to
would be using concatenation operator vector[WITH:0] = {(WITH+1)
{1'b1}};, which works for all WITH values.

Cheers,
Jim
http://myfpgablog.blogspot.com/

This is only part of what the standard says!

Yes simple decimal numbers are extended to integer width which must be
at least 32 bits, but you skipped the expression sizing rules where the
signed integer value will be sign extended to the larger of the R-value
or L-value width. It is then processed by the ~ operator which produces
a value that will always fill the vector with all 1 bits.

Cary

I could see that "-1" would be signed, and thus sign extended, but is
"~0" considered signed?

-- Gabor

 

[Cary R.]

On 12/16/2011 6:36 AM, Gabor wrote:

Cary R. wrote:
On 12/12/2011 8:53 PM, Jim Wu wrote:
On Dec 9, 12:03 pm, RolfK<Rolf.Kem...@renesas.com> wrote:
Dear Experts,

I have a simple question.
In verilog (2001) I use:

vector[WITH:0] = ~0 ;

to set all bits of a vector to 1.

This works fine in verilog for my RTL simulation.
But can I be sure that all nice syntheis and formal verifier tools
from big vendors like Synopsys and Cadence do understand this well ?
Does anybody have successfully used in some project ?

Thanks a lot for your feedback

Rolf

Unsized numbers are extended to 32-bit per Verilog LRM, so your code
only works if WITH<= 31. A better approach for what you're trying to
would be using concatenation operator vector[WITH:0] = {(WITH+1)
{1'b1}};, which works for all WITH values.

Cheers,
Jim
http://myfpgablog.blogspot.com/

This is only part of what the standard says!

Yes simple decimal numbers are extended to integer width which must be
at least 32 bits, but you skipped the expression sizing rules where
the signed integer value will be sign extended to the larger of the
R-value or L-value width. It is then processed by the ~ operator which
produces a value that will always fill the vector with all 1 bits.

Cary

I could see that "-1" would be signed, and thus sign extended, but is
"~0" considered signed?

-- Gabor

Page 8 1364-2001.

"Simple decimal numbers without the size and the base format shall be
treated as signed integers, ..."

So yes 0 is a signed number. ~ is just an operator and since it has a
signed operand the result will also be signed. The padding rules specify
that the 0 will be extended if the L-value is greater than the integer
width before it is processed by the ~ operator, but technically it would
give the same result if it was extended after the ~ since the result of
the ~ operator is also signed.

Cary

 

[unfrostedpoptart]

On Monday, December 12, 2011 8:53:44 PM UTC-8, Jim Wu wrote:

On Dec 9, 12:03 pm, RolfK <Rolf....@renesas.com> wrote:
Unsized numbers are extended to 32-bit per Verilog LRM, so your code
only works if WITH <= 31. A better approach for what you're trying to
would be using concatenation operator vector[WITH:0] = {(WITH+1)
{1'b1}};, which works for all WITH values.

This solution is probably the safest as far as making current simulation, lint, and synthesis tools happy and not giving you errors and warnings.

System Verilog added the '1, '0, 'x, and 'z unsized literals just for this purpose. Unfortunately, I've run into some tools that don't understand this syntax yet, so I've gone back to the replicate. Even for zero, which will extend correctly, some tools will give LHR/RHS size mismatch warnings so I just do something like this:

aaa = {($bits(aaa)){1'b0}}

which can be easily turned into the macro with arguments.

David