G
Guneet Singh
Guest
Hello everyone,
I am facing some problem with Verilog-AMS model simulation. I am
using the Cadence LDV-4.1 tool and trying to simulate a simple
resistor model with an analog control file (the test bench).
The first two steps (compilation and elaboration) are working fine
and I am not getting any errors. However when I simulate using ncsim,
I get an error. I am using using the resistor model that is in the
ncvlog manual just for checking whether the tool is working or not. I
am listing all the messages that I get when I execute the commands.
The hdl.var and cds.lib files are also included.
NCVLOG:
~/verilog11-9> ncvlog -ams -messages trial.vams
ncvlog: 04.10-s022: (c) Copyright 1995-2003 Cadence Design
Systems, Inc.
file: trial.vams
module worklib.restor:module
errors: 0, warnings: 0
NCELAB:
~/verilog11-9> ncelab -messages worklib.restor:module
ncelab: 04.10-s022: (c) Copyright 1995-2003 Cadence Design
Systems, Inc.
Elaborating the design hierarchy:
Discipline resolution Pass...
Building instance overlay tables: ....................
Done
Loading native compiled code: ....................
Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 1 1
Interconnect: 2 -
Writing initial simulation snapshot:
worklib.restor:module
Elaborating analog portion of the design hierarchy:
libsyracuse: @(#)$CDS: libsyracuse version
12/17/2003 03:11 (ncss21) $(sub-version 1217 )
NCSIM:
~/verilog11-9> ncsim -amslic -messages -analogcontrol trial.scs
worklib.restor:module
ncsim: 04.10-s022: (c) Copyright 1995-2003 Cadence Design
Systems, Inc.
Loading snapshot worklib.restor:module .................... Done
Starting analog simulation engine...
libpalermo: @(#)$CDS: libpalermo version
12/17/2003 03:11 (ncss21) $(sub-version 1217 )
Analog Kernel using -ANALOGCONTROL trial.scs.
Error found by spectre during circuit read-in.
trial.scs: RESTOR is an instance of an undefined model
restor.
spectre terminated prematurely due to fatal error.
ncsim: *E,RNAERR: Simulation is complete, analog initialization
error.
CDS.LIB:
INCLUDE /opt/CAD/Cadence/LDV-4.1/tools/inca/files/cds.lib
DEFINE worklib ./worklib
HDL.VAR:
SOFTINCLUDE $LDV-4.1/tools/inca/files/hdl.var
define ncuse5x
define cdslib ./cds.lib
DEFINE LIB_MAP (./ => worklib)
DEFINE worklib ./worklib
# Define view mapping.
# Files with .vb extension are compiled into view beh
# Files with .vr extension are compiled into view rtl
# Files with .vg extension are compiled into view gates
# Files with .vams extension are compiled into view module
DEFINE VIEW_MAP (.vb => beh, \
..vr => rtl, \
..vg => gates, \
..vams => module)
I am clueless as to why the simulator is not able to locate the
restor model. I would greatly appreciate if someone could suggest me a
solution to this problem.
Thanks and regards,
Guneet
I am facing some problem with Verilog-AMS model simulation. I am
using the Cadence LDV-4.1 tool and trying to simulate a simple
resistor model with an analog control file (the test bench).
The first two steps (compilation and elaboration) are working fine
and I am not getting any errors. However when I simulate using ncsim,
I get an error. I am using using the resistor model that is in the
ncvlog manual just for checking whether the tool is working or not. I
am listing all the messages that I get when I execute the commands.
The hdl.var and cds.lib files are also included.
NCVLOG:
~/verilog11-9> ncvlog -ams -messages trial.vams
ncvlog: 04.10-s022: (c) Copyright 1995-2003 Cadence Design
Systems, Inc.
file: trial.vams
module worklib.restor:module
errors: 0, warnings: 0
NCELAB:
~/verilog11-9> ncelab -messages worklib.restor:module
ncelab: 04.10-s022: (c) Copyright 1995-2003 Cadence Design
Systems, Inc.
Elaborating the design hierarchy:
Discipline resolution Pass...
Building instance overlay tables: ....................
Done
Loading native compiled code: ....................
Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 1 1
Interconnect: 2 -
Writing initial simulation snapshot:
worklib.restor:module
Elaborating analog portion of the design hierarchy:
libsyracuse: @(#)$CDS: libsyracuse version
12/17/2003 03:11 (ncss21) $(sub-version 1217 )
NCSIM:
~/verilog11-9> ncsim -amslic -messages -analogcontrol trial.scs
worklib.restor:module
ncsim: 04.10-s022: (c) Copyright 1995-2003 Cadence Design
Systems, Inc.
Loading snapshot worklib.restor:module .................... Done
Starting analog simulation engine...
libpalermo: @(#)$CDS: libpalermo version
12/17/2003 03:11 (ncss21) $(sub-version 1217 )
Analog Kernel using -ANALOGCONTROL trial.scs.
Error found by spectre during circuit read-in.
trial.scs: RESTOR is an instance of an undefined model
restor.
spectre terminated prematurely due to fatal error.
ncsim: *E,RNAERR: Simulation is complete, analog initialization
error.
CDS.LIB:
INCLUDE /opt/CAD/Cadence/LDV-4.1/tools/inca/files/cds.lib
DEFINE worklib ./worklib
HDL.VAR:
SOFTINCLUDE $LDV-4.1/tools/inca/files/hdl.var
define ncuse5x
define cdslib ./cds.lib
DEFINE LIB_MAP (./ => worklib)
DEFINE worklib ./worklib
# Define view mapping.
# Files with .vb extension are compiled into view beh
# Files with .vr extension are compiled into view rtl
# Files with .vg extension are compiled into view gates
# Files with .vams extension are compiled into view module
DEFINE VIEW_MAP (.vb => beh, \
..vr => rtl, \
..vg => gates, \
..vams => module)
I am clueless as to why the simulator is not able to locate the
restor model. I would greatly appreciate if someone could suggest me a
solution to this problem.
Thanks and regards,
Guneet