Verilog-AMS concatenations

[Paul Floyd]

Hi

I have a couple of language questions concerning concatenations.
Firstly, should Veriog-AMS perform bit concatenations like digital AMS?
E.g.,

integer i;
analog begin
i = {28'hfffffff,4'b1001};
end

Is this valid, with i being assigned 32'hfffffff9 ?

Secondly, other than as arguments to laplace/zi and noise_table, and as
default values for vector parameters, are there any other places where
it is legal to use a vector concatenation?

A bientot
Paul