verilog-AMS : always posedge support

[P. Kumar]

Hi,

I just started with Verilog-AMS, trying to combine digital and analog
behaviour. Since my own code didn't compile I Tried the sample code in
Chapter 11 of Verilog-AMS language reference, which is copied below also.
Even this code is giving me errors like always, posedge and reg are "future
reserved keywords".

Does, somebody know if they really future keywords are I am missing some
include file etc. I this is really not supported how can I include
normal(digital) verilog module inside Verilog-A.

regards
Parikshit

`include "constants.vams"
`include "disciplines.vams"

module sampler (in, clk, out);
inout in;
input clk;
output out;
electrical in; // "in" is a continuous net.
wire clk;
reg out;
always @(posedge clk) // Entering the discrete context.
out = V(in); // Access the continuous net.
endmodule

 

[Andrew Beckett]

On Mon, 19 Sep 2005 11:46:38 +0200, "P. Kumar" <reply@to.group> wrote:

Hi,

I just started with Verilog-AMS, trying to combine digital and analog
behaviour. Since my own code didn't compile I Tried the sample code in
Chapter 11 of Verilog-AMS language reference, which is copied below also.
Even this code is giving me errors like always, posedge and reg are "future
reserved keywords".

Does, somebody know if they really future keywords are I am missing some
include file etc. I this is really not supported how can I include
normal(digital) verilog module inside Verilog-A.

regards
Parikshit

`include "constants.vams"
`include "disciplines.vams"

module sampler (in, clk, out);
inout in;
input clk;
output out;
electrical in; // "in" is a continuous net.
wire clk;
reg out;
always @(posedge clk) // Entering the discrete context.
out = V(in); // Access the continuous net.
endmodule

Are you writing Verilog-A or Verilog-AMS? Verilog-A describes analogue
behaviour, whereas Verilog-AMS describes mixed-signal behaviour. posedge is for
discrete disciplines, which you don't have in Verilog-A (but do in Verilog-AMS).

So, to simulate Verilog-AMS you need to use AMS Designer - you can't use
spectre. spectre is an analogue-only simulator, and hence can simulate
Verilog-A. AMS Designer can simulate both.

I suspect you're trying the simulate the above Verilog-AMS module with spectre,
and it is quite rightly telling you that you're using keywords that it
understands are part of the standard, but it can't interpret (since they're not
Verilog-A).

Regards,

Andrew.