Verilog-A vector syntax

C

compact

Guest
Hi,
I'm wondering if the following vector expressions are Valid with
VerilogA:

_ branch (out[3],in[3]) net; // LRM says 'range' ??
_ V(out[3],in[3]) <+ I(out[3],in[3]);
_ I(<in[1]>)

Thanks for any inputs,
Lionel.
 

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