Verilog-A syntax error

[Samiran]

Hi all,

I have compiled the following piece of code:

******************************************************
if (V(vin_p,vin_n) > vin_max)
V(vout) <+ rampup*idt(1);
else if (V(vin_p,vin_n) < vin_min)
V(vout) <+ rampdown*idt(1);
******************************************************

And got the error:

***************************************************************************************************
analog operator `idt' embedded in conditionally executed statement or
expression.
***************************************************************************************************

How can I avoid this?

regards,
Sam

 

[Debjit]

On May 12, 1:34 am, Samiran <samiran....@gmail.com> wrote:

Hi all,

I have compiled the following piece of code:

******************************************************
if (V(vin_p,vin_n) > vin_max)
     V(vout) <+ rampup*idt(1);
else if (V(vin_p,vin_n) < vin_min)
     V(vout) <+ rampdown*idt(1);
******************************************************

And got the error:

***************************************************************************************************
analog operator `idt' embedded in conditionally executed statement or
expression.
***************************************************************************************************

How can I avoid this?

regards,
Sam

Dear Sam (Samiran),

You cannot embed idt statement within conditional statement. You can
do the following. Declare a real variable and assisgn idt(1) to that
real variable. Within the if statement, multiply that real variable
with rampdown or rampup. That will serve your purpose.
i.e.

real temp;
temp = idt(1);

if (V(vin_p,vin_n) > vin_max)
V(vout) <+ rampup*temp;
else if (V(vin_p,vin_n) < vin_min)
V(vout) <+ rampdown*temp;

This will serve your purpose.

Thanks and Regards !!!!

Cheers !!!!

Debjit.