Verilog 2's Complement Shifter

[Davy]

Hi all,

I am new to Verilog and want to build a 2's Complement Shifter.

I found
%displayb(8'b0001_1000>>2); //Output 0000_0110
%displayb(8'b1001_1000>>2); //Output 0010_0110

So >> is unsigned shift.
How can I build a signed (2's Complement) shift based on >>?
i.e. I want 8'b1001_1000>>2 //Output 1110_0110

Any suggestions will be appreciated!
Best regards,
Davy

 

[Spehro Pefhany]

On 6 Feb 2006 22:14:32 -0800, the renowned "Davy"
<zhushenli@gmail.com> wrote:

Hi all,

I am new to Verilog and want to build a 2's Complement Shifter.

I found
%displayb(8'b0001_1000>>2); //Output 0000_0110
%displayb(8'b1001_1000>>2); //Output 0010_0110

So >> is unsigned shift.
How can I build a signed (2's Complement) shift based on >>?
i.e. I want 8'b1001_1000>>2 //Output 1110_0110

Any suggestions will be appreciated!
Best regards,
Davy

Verilog 2001 has >>> (signed shift operator)


Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

 

[Alan Nishioka]

Davy wrote:

How can I build a signed (2's Complement) shift based on >>?
i.e. I want 8'b1001_1000>>2 //Output 1110_0110

How about
12'b1111_1001_1000>>2
or
{ 32{b[7]}, b } >> 2

 

[ALuPin@web.de]

WHY do Verilog users post in this newsgroup ?

Rgds
Andrés

 

But note that the so-called "signed shift" only gives you a signed or
arithmetic shift if it is used in a signed expression. In an unsigned
expression, you get an unsigned or logical shift. It isn't really a
"signed shift". It is a "shift using the signedness of the
expression". It is what the ordinary shift operator should have been
in the first place.