Verilog 2001 Port Declaration

  • Thread starter jjlindula@hotmail.com
  • Start date
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jjlindula@hotmail.com

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Hello, I'm new to Verilog and this should be a simple question for
others. I'm confused with the following:

// Verilog 2k with notype in port list
module memory_ansi_notype (
input read,
input write,
input [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
);

and this code:

// Verilog 2k with width and data type listed
module memory_ansi (
input wire read,
input wire write,
input wire [7:0] data_in,
input wire [3:0] addr,
output reg [7:0] data_out
);

I don't understand why 'wire' is used on the inputs, is there any
difference in the code.

Thanks,
joe

Thanks,
joe
 
On Tue, 24 Jun 2008 15:27:17 -0700 (PDT), "jjlindula@hotmail.com"
<jjlindula@hotmail.com> wrote:

Hello, I'm new to Verilog and this should be a simple question for
others. I'm confused with the following:

// Verilog 2k with notype in port list
module memory_ansi_notype (
input read,
input write,
input [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
);

and this code:

// Verilog 2k with width and data type listed
module memory_ansi (
input wire read,
input wire write,
input wire [7:0] data_in,
input wire [3:0] addr,
output reg [7:0] data_out
);

I don't understand why 'wire' is used on the inputs, is there any
difference in the code.
Click to expand...
Obviously, data_out is a net in the first port list and a
variable in the second port list. Otherwise, the two
port lists are identical unless you use the `default_nettype
directive. Ports without a "reg" or "wire" type get the current
default net type, which is "wire" unless you change it.

The most common situation where this matters is when someone has
used the directive
`default_nettype none
to suppress implicit declaration of sinlge-bit wires in port
connection lists.

Generally I would recommend including the "wire" keyword, to
protect yourself against someone else using `default_nettype
in a different file earlier in the same compilation run.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
On Jun 25, 1:29 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
On Tue, 24 Jun 2008 15:27:17 -0700 (PDT), "jjlind...@hotmail.com"



jjlind...@hotmail.com> wrote:
Hello, I'm new to Verilog and this should be a simple question for
others. I'm confused with the following:

// Verilog 2k with notype in port list
module memory_ansi_notype (
   input  read,
   input  write,
   input  [7:0] data_in,
   input  [3:0] addr,
   output  [7:0] data_out
 );

and this code:

// Verilog 2k with width and data type listed
 module memory_ansi (
   input wire read,
   input wire write,
   input wire [7:0] data_in,
   input wire [3:0] addr,
   output reg [7:0] data_out
 );

I don't understand why 'wire' is used on the inputs, is there any
difference in the code.

Obviously, data_out is a net in the first port list and a
variable in the second port list.  Otherwise, the two
port lists are identical unless you use the `default_nettype
directive.  Ports without a "reg" or "wire" type get the current
default net type, which is "wire" unless you change it.

The most common situation where this matters is when someone has
used the directive
  `default_nettype none
to suppress implicit declaration of sinlge-bit wires in port
connection lists.

Generally I would recommend including the "wire" keyword, to
protect yourself against someone else using `default_nettype
in a different file earlier in the same compilation run.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
Thanks Jonathan, I appreciate your time in taking to respond to my
post.
 
On Jun 25, 10:14 am, "jjlind...@hotmail.com" <jjlind...@hotmail.com>
wrote:
On Jun 25, 1:29 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com
wrote:



On Tue, 24 Jun 2008 15:27:17 -0700 (PDT), "jjlind...@hotmail.com"

jjlind...@hotmail.com> wrote:
Hello, I'm new to Verilog and this should be a simple question for
others. I'm confused with the following:

// Verilog 2k with notype in port list
module memory_ansi_notype (
input read,
input write,
input [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
);

and this code:

// Verilog 2k with width and data type listed
module memory_ansi (
input wire read,
input wire write,
input wire [7:0] data_in,
input wire [3:0] addr,
output reg [7:0] data_out
);

I don't understand why 'wire' is used on the inputs, is there any
difference in the code.

Obviously, data_out is a net in the first port list and a
variable in the second port list. Otherwise, the two
port lists are identical unless you use the `default_nettype
directive. Ports without a "reg" or "wire" type get the current
default net type, which is "wire" unless you change it.

The most common situation where this matters is when someone has
used the directive
`default_nettype none
to suppress implicit declaration of sinlge-bit wires in port
connection lists.

Generally I would recommend including the "wire" keyword, to
protect yourself against someone else using `default_nettype
in a different file earlier in the same compilation run.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Thanks Jonathan, I appreciate your time in taking to respond to my
post.
Click to expand...
The other thing to note is the output data_out, which in one case
is defined as type reg. In the old syntax you would write:

module memory_ansi (
read,
write,
data_in,
addr,
data_out
);

input read,
input write,
input [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
reg [7:0] data_out

Note the two line declaration for data_out. In the 2001
syntax you will get an error if you define data_out as
output in the port list, and then add a reg definition in
the code body. So in the first of your two cases data_out
will specifically not be of type reg.

Regards,
Gabor
 
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