verilog 2001 partial variable select (help needed)

[rootz]

Hi.
I would like to dynamically select certain bits in a bus.
For example if I have a 64-bit bus test_data[63:0], I would like to be
able to select a subset of test_data[x:y] where both x and y can be
known at run-time. I heard this was possible in verilog 2001 for some
synthesis tools.
Any comments?

 

[Allan Herriman]

On 1 Feb 2005 19:21:06 -0800, "rootz" <kgyang@gmail.com> wrote:

Hi.
I would like to dynamically select certain bits in a bus.
For example if I have a 64-bit bus test_data[63:0], I would like to be
able to select a subset of test_data[x:y] where both x and y can be
known at run-time. I heard this was possible in verilog 2001 for some
synthesis tools.
Any comments?

These are known as 'indexed part selects'.

test_data[y +: width], where width is constant at compile time.

I don't think this is widely supported by synthesis tools yet.

Regards,
Allan

 

[John_H]

If the values are known at run time, use parameters or localparams for the x
and y values. No Verilog2001 needed.
localparam x = 12'hcab;

"rootz" <kgyang@gmail.com> wrote in message
news:1107314466.669615.218160@z14g2000cwz.googlegroups.com...

Hi.
I would like to dynamically select certain bits in a bus.
For example if I have a 64-bit bus test_data[63:0], I would like to be
able to select a subset of test_data[x:y] where both x and y can be
known at run-time. I heard this was possible in verilog 2001 for some
synthesis tools.
Any comments?

 

You can use an indexed part select to select a bit
field using a variable expression for the starting bit.
The width of the field must still be a compile-time
constant. The syntax is test_data[y +: width] or
test_data[x -: width], assuming y is the smaller
number, and x = y + width - 1.

You will have to find out whether your tools support
this. If they don't, the usual workaround is to use a
shift: (test_data >> y).