Verilog 2001 coding style question

[Marco Lazar]

Hi,

i want to write a parameterizable module with the least amount
of coding. Below code is what i got and VCS compiles it just fine:

module dummy (
input_a,
input_b,
output_a
);

// parameters
parameter WIDTH_A = 32;
parameter WIDTH_B = 64;

// Interfaces
input [(WIDTH_A-1) : 0] input_a;
input [(WIDTH_B-1) : 0] input_b;
output [(WIDTH_A-1) : 0] output_a;

// do something
...
...
...

endmodule


Still, i don't want to have to declare all the inputs and outputs
in the module declaration and then define them later on. I know in
V2k you can combine these into one statement and put them into the
module declaration part. But how does it work with inputs and outputs
whose width are parameterizable ? So can i do something like this:

module dummy (
parameter WIDTH_A = 32;
parameter WIDTH_B = 64;

// Interfaces
input [(WIDTH_A-1) : 0] input_a;
input [(WIDTH_B-1) : 0] input_b;

output [(WIDTH_A-1) : 0] output_a;
output [(WIDTH_B-1) : 0] output_b;

);


// do something
...
...
...

endmodule

Thanks in advance for your help !!

 

[Steven Sharp]

Marco Lazar <lazar@hou.asp.ti.com> wrote in message news:<bup5b5$q3p$1@newshost.hou.asp.ti.com>...

Still, i don't want to have to declare all the inputs and outputs
in the module declaration and then define them later on. I know in
V2k you can combine these into one statement and put them into the
module declaration part. But how does it work with inputs and outputs
whose width are parameterizable ? So can i do something like this:

You declare the parameters in a separate parenthesized list preceded
by a #. This matches how you instantiate a module, where the parameter
override values are in a separate parenthesized list preceded by a #.
Also, items in ANSI-C style port lists are separated by commas, not
terminated by semicolons. There are no semicolons used in the lists.

So for example:

module dummy #(parameter WIDTH_A = 32, WIDTH_B = 64)
(
// Interfaces
input [(WIDTH_A-1) : 0] input_a,
input [(WIDTH_B-1) : 0] input_b,

output [(WIDTH_A-1) : 0] output_a,
output [(WIDTH_B-1) : 0] output_b

);