Verifying output data is sorted by looking at the signal

M

maja55

Guest
I have a odd-even transposition sort program in Verilog. Running the simulation, how can I verify the sorting by referring to the input and output signals?
 
I performed a behavioral simulation of the odd-even transposition design [code below] in Verilog. Using the waveform viewer, zoomed in to an appropriate level. How can I evaluate the relationship of the input values to the output values? For inputs applied on a given cycle, how can I identify the corresponding outputs from the circuit.
How can I verify the design appear to correctly sort the input data?

`timescale 1ns / 1ps
module sort (
input wire clk,
input wire [15:0] in1, in2, in3, in4, in5,
output reg [15:0] out1, out2, out3, out4, out5
);

reg [15:0] dat1, dat2, dat3, dat4, dat5;
always @(posedge clk)
begin
dat1 <= in1;
dat2 <= in2;
dat3 <= in3;
dat4 <= in4;
dat5 <= in5;
end

integer i, j;
reg [15:0] temp;
reg [15:0] array [1:5];
always @*
begin
array[1] = dat1;
array[2] = dat2;
array[3] = dat3;
array[4] = dat4;
array[5] = dat5;

for (i = 5; i > 0; i = i - 1)
begin
for (j = 1 ; j < i; j = j + 1)
begin
if (array[j] < array[j + 1])
begin
temp = array[j];
array[j] = array[j + 1];
array[j + 1] = temp;
end
end
end
end

always @(posedge clk)
begin
out1 <= array[1];
out2 <= array[2];
out3 <= array[3];
out4 <= array[4];
out5 <= array[5];
end
endmodule
 
On Thursday, November 20, 2014 4:17:13 PM UTC-8, gabor wrote:
On 11/20/2014 6:21 PM, maja55 wrote:
I performed a behavioral simulation of the odd-even transposition design [code below] in Verilog. Using the waveform viewer, zoomed in to an appropriate level. How can I evaluate the relationship of the input values to the output values? For inputs applied on a given cycle, how can I identify the corresponding outputs from the circuit.
How can I verify the design appear to correctly sort the input data?

`timescale 1ns / 1ps
module sort (
input wire clk,
input wire [15:0] in1, in2, in3, in4, in5,
output reg [15:0] out1, out2, out3, out4, out5
);

reg [15:0] dat1, dat2, dat3, dat4, dat5;
always @(posedge clk)
begin
dat1 <= in1;
dat2 <= in2;
dat3 <= in3;
dat4 <= in4;
dat5 <= in5;
end

integer i, j;
reg [15:0] temp;
reg [15:0] array [1:5];
always @*
begin
array[1] = dat1;
array[2] = dat2;
array[3] = dat3;
array[4] = dat4;
array[5] = dat5;

for (i = 5; i > 0; i = i - 1)
begin
for (j = 1 ; j < i; j = j + 1)
begin
if (array[j] < array[j + 1])
begin
temp = array[j];
array[j] = array[j + 1];
array[j + 1] = temp;
end
end
end
end

always @(posedge clk)
begin
out1 <= array[1];
out2 <= array[2];
out3 <= array[3];
out4 <= array[4];
out5 <= array[5];
end
endmodule


The sorting code appears to be all combinatorial. So you just
have one cycle delay from the inputs to the dat1 through dat5 regs
and another cycle delay from the array[x] to the out1 through out5
regs. So the outputs should be the sort of the inputs after exactly
2 clock cycles.

It's hard to imagine how you'd check this for correctness in the
test bench without having another sorting algorithm in the test
bench itself. On the other hand if you are willing to pore through
the waveform, it would at least help to generate a two-cycle delay
of the 5 module inputs so they will line up with ouputs.

--
Gabor
Click to expand...

Simulation images:
https://drive.google.com/file/d/0B6o4BMKK8QTMTElYUzhlM2R0cTg/view?usp=sharing
https://drive.google.com/file/d/0B6o4BMKK8QTMa0FtejZYQ0liWHc/view
https://drive.google.com/file/d/0B6o4BMKK8QTMeEs1Qlo1ZWFyWHM/view
 
On 11/20/2014 6:21 PM, maja55 wrote:
in Verilog. Using the waveform viewer, zoomed in to an appropriate level. How can I evaluate the relationship of the input values to the output values? For inputs applied on a given cycle, how can I identify the corresponding outputs from the circuit.
How can I verify the design appear to correctly sort the input data?

`timescale 1ns / 1ps
module sort (
input wire clk,
input wire [15:0] in1, in2, in3, in4, in5,
output reg [15:0] out1, out2, out3, out4, out5
);

reg [15:0] dat1, dat2, dat3, dat4, dat5;
always @(posedge clk)
begin
dat1 <= in1;
dat2 <= in2;
dat3 <= in3;
dat4 <= in4;
dat5 <= in5;
end

integer i, j;
reg [15:0] temp;
reg [15:0] array [1:5];
always @*
begin
array[1] = dat1;
array[2] = dat2;
array[3] = dat3;
array[4] = dat4;
array[5] = dat5;

for (i = 5; i > 0; i = i - 1)
begin
for (j = 1 ; j < i; j = j + 1)
begin
if (array[j] < array[j + 1])
begin
temp = array[j];
array[j] = array[j + 1];
array[j + 1] = temp;
end
end
end
end

always @(posedge clk)
begin
out1 <= array[1];
out2 <= array[2];
out3 <= array[3];
out4 <= array[4];
out5 <= array[5];
end
endmodule
Click to expand...

The sorting code appears to be all combinatorial. So you just
have one cycle delay from the inputs to the dat1 through dat5 regs
and another cycle delay from the array[x] to the out1 through out5
regs. So the outputs should be the sort of the inputs after exactly
2 clock cycles.

It's hard to imagine how you'd check this for correctness in the
test bench without having another sorting algorithm in the test
bench itself. On the other hand if you are willing to pore through
the waveform, it would at least help to generate a two-cycle delay
of the 5 module inputs so they will line up with ouputs.

--
Gabor
 
On 11/20/2014 8:00 PM, maja55 wrote:
On Thursday, November 20, 2014 4:17:13 PM UTC-8, gabor wrote:
On 11/20/2014 6:21 PM, maja55 wrote:
I performed a behavioral simulation of the odd-even transposition design [code below] in Verilog. Using the waveform viewer, zoomed in to an appropriate level. How can I evaluate the relationship of the input values to the output values? For inputs applied on a given cycle, how can I identify the corresponding outputs from the circuit.
How can I verify the design appear to correctly sort the input data?

`timescale 1ns / 1ps
module sort (
input wire clk,
input wire [15:0] in1, in2, in3, in4, in5,
output reg [15:0] out1, out2, out3, out4, out5
);

reg [15:0] dat1, dat2, dat3, dat4, dat5;
always @(posedge clk)
begin
dat1 <= in1;
dat2 <= in2;
dat3 <= in3;
dat4 <= in4;
dat5 <= in5;
end

integer i, j;
reg [15:0] temp;
reg [15:0] array [1:5];
always @*
begin
array[1] = dat1;
array[2] = dat2;
array[3] = dat3;
array[4] = dat4;
array[5] = dat5;

for (i = 5; i > 0; i = i - 1)
begin
for (j = 1 ; j < i; j = j + 1)
begin
if (array[j] < array[j + 1])
begin
temp = array[j];
array[j] = array[j + 1];
array[j + 1] = temp;
end
end
end
end

always @(posedge clk)
begin
out1 <= array[1];
out2 <= array[2];
out3 <= array[3];
out4 <= array[4];
out5 <= array[5];
end
endmodule


The sorting code appears to be all combinatorial. So you just
have one cycle delay from the inputs to the dat1 through dat5 regs
and another cycle delay from the array[x] to the out1 through out5
regs. So the outputs should be the sort of the inputs after exactly
2 clock cycles.

It's hard to imagine how you'd check this for correctness in the
test bench without having another sorting algorithm in the test
bench itself. On the other hand if you are willing to pore through
the waveform, it would at least help to generate a two-cycle delay
of the 5 module inputs so they will line up with ouputs.

--
Gabor

Simulation images:
https://drive.google.com/file/d/0B6o4BMKK8QTMTElYUzhlM2R0cTg/view?usp=sharing
https://drive.google.com/file/d/0B6o4BMKK8QTMa0FtejZYQ0liWHc/view
https://drive.google.com/file/d/0B6o4BMKK8QTMeEs1Qlo1ZWFyWHM/view
Click to expand...

If you're planning to use the waveform view to debug this, the
first recommendation I'd make is to change the radix to hexadecimal
or even decimal. I don't know about you, but I have a hard time
determining if two long binary numbers are the same.

--
Gabor
 
On Thursday, November 20, 2014 6:05:30 PM UTC-8, gabor wrote:
On 11/20/2014 8:00 PM, maja55 wrote:
On Thursday, November 20, 2014 4:17:13 PM UTC-8, gabor wrote:
On 11/20/2014 6:21 PM, maja55 wrote:
I performed a behavioral simulation of the odd-even transposition design [code below] in Verilog. Using the waveform viewer, zoomed in to an appropriate level. How can I evaluate the relationship of the input values to the output values? For inputs applied on a given cycle, how can I identify the corresponding outputs from the circuit.
How can I verify the design appear to correctly sort the input data?

`timescale 1ns / 1ps
module sort (
input wire clk,
input wire [15:0] in1, in2, in3, in4, in5,
output reg [15:0] out1, out2, out3, out4, out5
);

reg [15:0] dat1, dat2, dat3, dat4, dat5;
always @(posedge clk)
begin
dat1 <= in1;
dat2 <= in2;
dat3 <= in3;
dat4 <= in4;
dat5 <= in5;
end

integer i, j;
reg [15:0] temp;
reg [15:0] array [1:5];
always @*
begin
array[1] = dat1;
array[2] = dat2;
array[3] = dat3;
array[4] = dat4;
array[5] = dat5;

for (i = 5; i > 0; i = i - 1)
begin
for (j = 1 ; j < i; j = j + 1)
begin
if (array[j] < array[j + 1])
begin
temp = array[j];
array[j] = array[j + 1];
array[j + 1] = temp;
end
end
end
end

always @(posedge clk)
begin
out1 <= array[1];
out2 <= array[2];
out3 <= array[3];
out4 <= array[4];
out5 <= array[5];
end
endmodule


The sorting code appears to be all combinatorial. So you just
have one cycle delay from the inputs to the dat1 through dat5 regs
and another cycle delay from the array[x] to the out1 through out5
regs. So the outputs should be the sort of the inputs after exactly
2 clock cycles.

It's hard to imagine how you'd check this for correctness in the
test bench without having another sorting algorithm in the test
bench itself. On the other hand if you are willing to pore through
the waveform, it would at least help to generate a two-cycle delay
of the 5 module inputs so they will line up with ouputs.

--
Gabor

Simulation images:
https://drive.google.com/file/d/0B6o4BMKK8QTMTElYUzhlM2R0cTg/view?usp=sharing
https://drive.google.com/file/d/0B6o4BMKK8QTMa0FtejZYQ0liWHc/view
https://drive.google.com/file/d/0B6o4BMKK8QTMeEs1Qlo1ZWFyWHM/view


If you're planning to use the waveform view to debug this, the
first recommendation I'd make is to change the radix to hexadecimal
or even decimal. I don't know about you, but I have a hard time
determining if two long binary numbers are the same.

--
Gabor
Click to expand...

How can I check the input and its corresponding output looking at the signal?
 
On Friday, November 21, 2014 8:44:36 PM UTC, maja55 wrote:
> How can I check the input and its corresponding output looking at the signal?

You need to write a testbench that drives some stimulus into your design and checks that the outputs are correct. There are many ways to write a testbench, I happen to be a little biased but I think the quickest and most effective way is using Python:

for values in data_generator(bits=len(dut.in1)):
expected.append(sorted(values))

yield RisingEdge(dut.clk)
dut.in1 = values[0]
dut.in2 = values[1]
dut.in3 = values[2]
dut.in4 = values[3]
dut.in5 = values[4]

yield ReadOnly()
expect = expected.pop(0)

if expect is None: continue

got = [int(dut.out5), int(dut.out4), int(dut.out3),
int(dut.out2), int(dut.out1)]

if got != expect:
dut.log.error('Expected %s' % expect)
dut.log.error('Got %s' % got)
raise TestFailure("Output didn't match")

Full working testbench on github: https://github.com/chiggs/comp.lang.verilog/blob/master/maja55/testbench.py
 
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