verification vs validation

P

pradeep

Guest
Hi,

can any one give the difference between verification and validation ?

what is system level validation ?

what is emulation ?

with regards
pradeep.g
 
pradeep wrote:
Hi,

can any one give the difference between verification and validation ?

Will I get credit for doing your assignments?

what is system level validation ?

What is homework?

what is emulation ?
Why can't you read your text book?


I don't normally answer posts that appear to be students asking for help
with homework (or more correctly asking others to do the work for
them). But this is just too obvious.

How about you read your book and write a couple of paragraphs on each of
the above questions for us to critique? Wouldn't that be more useful to
you?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
hi rick,

i am sorry for asking these type of trivial questions,

let me be the first person to answer.

Difference between verification and validation

Validation and verification refer to the process of satisfying the
requirement, but the difference lies in the level of testing.

Verification refer to lower level of test, like testing of module,
interface etc. Verification tests are conducted by the developer.

Whereas validation occurs at the final stage prior to the acceptance
of a product for release. Validation tests are normally conducted by a
party that is independent of the developer (Quality Assurance or the
test group)

Emulation

The process by which a device is built to work like another. For
example, a chip can be designed to emulate another model. The emulator
can be hardware, software or both



with regards
pradeep.g



rickman <spamgoeshere4@yahoo.com> wrote in message news:<3FBDA0A6.BF7DDCA3@yahoo.com>...
pradeep wrote:

Hi,

can any one give the difference between verification and validation ?

Will I get credit for doing your assignments?

what is system level validation ?

What is homework?

what is emulation ?

Why can't you read your text book?


I don't normally answer posts that appear to be students asking for help
with homework (or more correctly asking others to do the work for
them). But this is just too obvious.

How about you read your book and write a couple of paragraphs on each of
the above questions for us to critique? Wouldn't that be more useful to
you?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
pradeep wrote:
hi rick,

i am sorry for asking these type of trivial questions,

let me be the first person to answer.

Difference between verification and validation

Validation and verification refer to the process of satisfying the
requirement, but the difference lies in the level of testing.

Verification refer to lower level of test, like testing of module,
interface etc. Verification tests are conducted by the developer.

Whereas validation occurs at the final stage prior to the acceptance
of a product for release. Validation tests are normally conducted by a
party that is independent of the developer (Quality Assurance or the
test group)
Looking at the definition of those two words, you could just as easily
reverse the wording of the last two paragraphs and you would be equally
correct.

The company I work for has a group called DVT (design verification and
test). They are the high level testers... the final stage prior to
product release. I'll bet others in the group have similar "final test"
groups that use the word validation rather than verification.

In my opinion, the words have close enough meanings that confusion would
result if an organization tried to use them, by themselves, to mean two
different things.

Have fun,

Marc
 
Verification proves (or at least, attempts to prove) that the design meets
the specification.
Validation proves that original specification was sound.

Check out www.dictionary.com

--
Ian Poole, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: ian.poole@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.


"Marc Randolph" <mrand@my-deja.com> wrote in message
news:_Ppvb.2138$n15.1506@newssvr24.news.prodigy.com...
pradeep wrote:
hi rick,

i am sorry for asking these type of trivial questions,

let me be the first person to answer.

Difference between verification and validation

Validation and verification refer to the process of satisfying the
requirement, but the difference lies in the level of testing.

Verification refer to lower level of test, like testing of module,
interface etc. Verification tests are conducted by the developer.

Whereas validation occurs at the final stage prior to the acceptance
of a product for release. Validation tests are normally conducted by a
party that is independent of the developer (Quality Assurance or the
test group)

Looking at the definition of those two words, you could just as easily
reverse the wording of the last two paragraphs and you would be equally
correct.

The company I work for has a group called DVT (design verification and
test). They are the high level testers... the final stage prior to
product release. I'll bet others in the group have similar "final test"
groups that use the word validation rather than verification.

In my opinion, the words have close enough meanings that confusion would
result if an organization tried to use them, by themselves, to mean two
different things.

Have fun,

Marc
 

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