verification tools?

[burn.sir@spam-me-not-gmai]

hello group! (and sorry for the cross-posting)

I am working on a complex FPGA prototype and have already a feeling
that the usual "testbench verification" wont help very much here. I
have worked with formal verification in past and think this is a great
opportunity to introduce the team to FV.

I couldn't get the management to pay for new verification software, so
i decided to ask the experts (you guys) if any good but "free"
verification tools are available. I am even interested in academic type
of software (=working but user unfriendly). For example, i could go for
SMV if i could figure out a way to feed it VHDL or compiled netlists.

Of course, it does not have to be "formal" verification. I could go
with any tool available as long as it gets the job done. So please help
me find the right tool for this job. You may also take this as a great
opportunity for you guys to promote your software or share your
experiences with the world!

regards, Burns

 

[Tom]

In terms of free model checkers, I've had the best luck with NuSMV. It
doesn't have an HDL front-end, but does support a subset of PSL. There
is a path to get Verilog into NuSMV using Icarus and Confluence's
netlister (FNF), but the Verilog front-end is bit out of date.

A better option is HDCaml. It already has a builtin simulator; once
the link to NuSMV is completed, any counter example would produce VCD
waveforms for debugging. HDCaml already generates synthesizable
Verilog and SystemC. You'll find both the Icarus-FNF-NuSMV tool
chain and the HDCaml HDL here...

http://www.confluent.org/

Of course if money's no object, I recommend Cadence IFV.

-Tom