A
Ani
Guest
I have just created behavioral level verilog models of some circuits
and want to compare these with existing gate level models to ensure
functional equivalence. How do I do this? I tried to use Mentor
Graphics Formal Pro but somehow I'm convinced I'm doing something wrong
there....Has anybody used this software before?
and want to compare these with existing gate level models to ensure
functional equivalence. How do I do this? I tried to use Mentor
Graphics Formal Pro but somehow I'm convinced I'm doing something wrong
there....Has anybody used this software before?