Verification by Non-HDL(C++/Java)??

[Davy]

Hi all,

I found that some verification procedure using Non-HDL such as
C++/Java.

But how these Non-HDL language generate edge stimulus? Can Non-HDL also
generate @posedage???

Is there any basic idea behind it?

Best regards,
Davy

 

[naren]

Davy wrote:

Hi all,

I found that some verification procedure using Non-HDL such as
C++/Java.

But how these Non-HDL language generate edge stimulus? Can Non-HDL also
generate @posedage???

Is there any basic idea behind it?

Best regards,
Davy

Hi Davy,
They do it through an interface called VHPI (for VHDL) or PLI (for
verilog). A quick googling should give you decent links.
You could also write t/b's in perl / python et.al...
Thanks,
Naren.

 

[Hans]

and you might also want to look at SystemC which, IMHO, is easier to
interface to Verilog/VHDL.

Hans
www.ht-lab.com


"naren" <narenkn@gmail.com> wrote in message
news:1147277907.156587.75050@j33g2000cwa.googlegroups.com...

Davy wrote:

Hi all,

I found that some verification procedure using Non-HDL such as
C++/Java.

But how these Non-HDL language generate edge stimulus? Can Non-HDL also
generate @posedage???

Is there any basic idea behind it?

Best regards,
Davy

Hi Davy,
They do it through an interface called VHPI (for VHDL) or PLI (for
verilog). A quick googling should give you decent links.
You could also write t/b's in perl / python et.al...
Thanks,
Naren.

 

[Srinivasan Venkataramanan]

Davy,
Try http://teal.sf.net

Though I would rather use SystemVerilog for the same.

Good Luck
Ajeetha, CVC
www.noveldv.com

 

[mmintz@gmail.com]

Hi Davy,

I am the creator to teal. Let me know if I can help in any way.

I am also real close to releasing a verification framework in C++.

Take Care,
Mike